AD1843JS datasheet(48/64 Pages) AD

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AD1843

Address 27

Codec Configuration—Channel Power Down

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DFREE

res

DDMEN

res

DA2EN

DA1EN

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

ANAEN

HPEN

res

AAMEN

res

ADREN

ADLEN

DFREE

Digital Resource Free. When set to “1,” this bit reduces the level of power down normally achieved by asserting the

power down bits in this Control Register. However, it allows the digital resources of channels powered down to be

partially transferred to the remaining enabled channels and thus permits conversion rates higher than the 48 kHz

nominal maximum. See the “Supported Conversion Rates” section.

0 = Power Down of Digital Resources is Complete

1 = Power Down of Digital Resources is Incomplete, Freeing Transferable Resources to Enabled Channels

DDMEN

DAC2 to DAC1 Mix Enable/Power Down. When reset to “0,” Control Register Address 3 is cleared to its default

and cannot be written.

0 = Mix is Powered Down

1 = Mix is Enabled

DA2EN

DAC2 (Left and Right Channels) Enable/Power Down. When this bit is reset to “0,” DAC2 is powered down and

serial interface requests for samples (see slot 0) will cease immediately. When this bit is set to “1,” DAC2 is enabled

and requests for samples resume on the next frame. Conversions will not actually begin until the first rising edge of

the conversion clock (CONV pin) after the sixth rising edge of frame sync (SDFS pin) after this bit is set to “1.” This

delay allows the four word stereo input buffer for DAC2 to be filled before conversions begin and allows the serial in-

terface to synchronize with the conversion clock, which is potentially already running. This delay also allows DACs

on multiple AD1843s sharing the same frame sync to begin conversions synchronously, providing they are enabled at

any time during the same frame. When this bit is reset to “0,” Control Register Address 10, which is the Output

Level Control Register for DAC2, is cleared to default and cannot be written.

0 = DAC2 is Powered Down, Control Register Address 10 (DAC2 Output Level Control) is Cleared

1 = DAC2 is Enabled

DA1EN

DAC1 (Left and Right Channels) Enable/Power Down. When this bit is reset to “0,” DAC1 is powered down and

serial interface requests for samples (see slot 0) will cease immediately. When this bit is set to “1,” DAC1 is enabled

and requests for samples resume on the next frame. Conversions will not actually begin until the first rising edge of

the conversion clock (CONV pin) after the sixth rising edge of frame sync (SDFS pin) after this bit is set to “1.” This

delay allows the four word stereo input buffer for DAC1 to be filled before conversions begin and allows the serial in-

terface to synchronize with the conversion clock, which is potentially already running. This delay also allows DACs

on multiple AD1843s sharing the same frame sync to begin conversions synchronously, providing they are enabled at

any time during the same frame. When this bit is reset to “0,” Control Register Address 9, which is the Output Level

Control Register for DAC1, is cleared to default and cannot be written.

0 = DAC1 is Powered Down, Control Register Address 9 (DAC1 Output Level Control) is Cleared

1 = DAC1 is Enabled

ANAEN

Analog Channel Enable/Power Down. If this bit is reset to “0,” all analog conversion circuitry (related to bits

DA1EN, DA2EN, ADLEN, ADREN, DDMEN and AAMEN) will be powered down. When reset to “0,” the only

conversion channels usable (but must be enabled separately) are the digital resampling paths. Since resetting this bit

to “0” powers down the analog ADC, DAC1, DAC2 and analog mixers, their related output level Control Register

Addresses 4 through 7, half of 8, 9 and 10 are cleared and cannot be written while ANAEN remains “0.”

0 = Analog Channels are Powered Down, Control Register Addresses 4 through 7, half of 8, 9 and 10 are Cleared to

Default (Digital to Digital Still Possible)

1 = Analog DAC and ADC Paths are Controlled by DA1EN, DA2EN, ADLEN, ADREN, DDMEN and AAMEN

HPEN

Headphone Enable/Power Down.

0 = Headphone Output is Powered Down

1 = Headphone Output is Enabled

AAMEN

Analog Input to Analog Output Mix Enable/Power Down. When reset to “0,” Control Register Addresses 4 - 7 and

half of Control Register Address 8 are cleared and cannot be written.

0 = Mix is Powered Down

1 = Mix is Enabled

AD1843JS Datasheet(PDF) 48 Page - Analog Devices

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