AD1843JS datasheet(50/64 Pages) AD

50 / 64 page

REV. 0

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AD1843

C2EN

Clock Generator 2 Enable/Power Down.

0 = Clock Generator 2 Powered Down

1 = Clock Generator 2 Enabled

C1EN

Clock Generator 1 Enable/Power Down.

0 = Clock Generator 1 Powered Down

1 = Clock Generator 1 Enabled

ENCLKO

CLKOUT Pin Enable.

0 = Clock Output is Three-stated (Powered Down)

1 = Clock Output is Enabled

XCTL1:0

External Control. The state of these independent bits is reflected on the respective XCTL1 and XCTL0 output pins.

0 = TTL Logic Level LO on XCTL1/XCTL0 pin

1 = TTL Logic Level HI on XCTL1/XCTL0 pin

ENCV3

CONV3 Pin Enable.

0 = CONV3 is Three-stated (Powered Down)

1 = CONV3 is Enabled

ENBT3

BIT3 Pin Enable.

0 = BIT3 is Three-stated (Powered Down)

1 = BIT3 is Enabled

ENCV2

CONV2 Pin Enable.

0 = CONV2 is Three-stated (Powered Down)

1 = CONV2 is Enabled

ENBT2

BIT2 Pin Enable.

0 = BIT2 is Three-stated (Powered Down)

1 = BIT2 is Enabled

ENCV1

CONV1 Pin Enable.

0 = CONV1 is Three-stated (Powered Down)

1 = CONV1 is Enabled

ENBT1

BIT1 Pin Enable.

0 = BIT1 is Three-stated (Powered Down)

1 = BIT1 is Enabled

LINRSD

Line Input Right Channel Single-Ended or Differential Configuration.

0 = Right Channel Line Input is Single-Ended

1 = Right Channel Line Input is Differential

LINLSD

Line Input Left Channel Single-Ended or Differential Configuration.

0 = Left Channel Line Input is Single-Ended

1 = Left Channel Line Input is Differential

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1100 0100 0000 0000 (C400 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

Address 29

Reserved for Future Expansion

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

AD1843JS Datasheet(PDF) 50 Page - Analog Devices

AD1843JS Datasheet(HTML) 50 Page - Analog Devices

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