AD1843JS datasheet(43/64 Pages) AD

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AD1843

REV. 0

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1 = Clocks are referenced to the input on pin SYNC3 (Sync 3 Clock Input).

Sample clock frequency is defined by C3VID and C3M7:0.

Sample clock phase is locked to SYNC3 and cannot be shifted.

Bit clock frequency is defined by bits C3M7:0 and C3P200 unless in Video Lock Mode

(C3VID set to “1”) where the Bit clocks are not produced.

Control Register Addresses 23, 24 and the C3X8/7 bits are ignored.

C3VID

Clock Generator 3 Video Lock Mode. This bit is used to select between lock modes when the Clock Generator 3 is

referenced to SYNC3 (C3REF set to “1”). This bit should be reset to “0” if C3REF is reset to “0.” When reset to

“0,” Clock Generator 3 is in normal lock mode where the Conversion clock will be frequency and phase locked to

SYNC3, and the Bit clock frequency is chosen using bits C3M7:0 and C3P200. When set to “1,” Clock Generator 3

is in video lock mode, where the Conversion clock frequency is selected using bits C3M7:0, and a Bit clock is not produced.

C3PLLG

Clock Generator 3 PLL Loop Gain Select. If reset to “0,” this bit selects finite PLL loop gain, and if set to “1,” this

bit selects infinite PLL loop gain. This bit should nominally be reset to “0.” Setting it to “1” may enhance the PLL’s

ability to lock to certain SYNC3 inputs, but it may also increase conversion noise.

C3P200

Clock Generator 3 Bit Clock +200 Frequency Modifier. When set to “1,” the Bit clock driven out of pin BIT3 will

have a frequency that is 200 Hertz greater than the frequency selected through bit C3M7:0. This bit is ignored when

in Video Lock Mode (C3VID set to “1”). C3P200 only modifies the bit clock driven on the BIT3 pin.

C3X8/7

Clock Generator 3 Conversion Clock 8/7 Frequency Modifier. When set to “1,” the Conversion clock frequency gen-

erated will be 8/7 times the value programmed in Control Register Address 23. This bit is ignored when clocks are

referenced to SYNC3 (C3REF set to “1”).

C3C128

Clock Generator 3 Conversion Clock Pin (CONV3) Frequency Select. When set to “1,” the frequency driven on to

the CONV3 pin will be 128 times the conversion rate. When reset to “0,” the frequency driven on to the CONV3 pin

will be the same as the conversion rate. C3C128 only modifies the clock frequency driven on the CONV3 pin.

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

C3M7:0

Clock Generator 3 Clock Rate Modifiers.

When not in Video Lock Mode (C3REF and C3VID are not both set to “1”):

Bits C3M7:0 select the Bit clock rate which will be driven out on pin BIT3. Using the following table, the least sig-

nificant four bits (C3M3:0) are programmed to the desired Bit clock rate, and the most significant four bits

(C3M7:4) must be programmed to the Conversion clock rate established using Control Register Address 23 and the

C3X8/7 bit. If the actual Conversion clock differs from the value selected by C3M7:4, then the resultant Bit clock

will be different from the rate selected by the ratio of the C3M7:4 selected rate to the Control Register Address 23

plus the C3X8/7 bit actual rate.

C3M3:0

Bit Clock Frequency*

C3M7:4

Conversion (Sample) Rate

0000

2,400

Hertz

0000

7,200

Hertz

0001

4,800

0001

8,400

0010

7,200

0010

9,000

0011

9,600

0011

9,600

0100

12,000

0100

11,200

0101

14,400

0101

12,000

0110

16,800

0110

12,800

0111

19,200

0111

7,200

× 8/7

1000

21,600

1000

9,000

× 8/7

1001

24,000

1001

9,600

× 8/7

1010

26,400

1010

12,000

× 8/7

1011

28,800

1011

Reserved

1100

Reserved

1100

Reserved

1101

Reserved

1101

Reserved

1110

Reserved

1110

Reserved

1111

See Below

1111

See Below

*Bit clock frequencies listed will be increased by 200 Hz if C3P200 is set to “1.”

When C3M7:4 is programmed to “1111” and C3M3:0 is programmed to “1111,” the Bit clock rate will be 128 times

the Conversion rate.

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