AD1843JS datasheet(7/64 Pages) AD

7 / 64 page

AD1843

REV. 0

–7–

PIN CONFIGURATIONS

80-Lead PQFP

AD1843

TOP VIEW

(Not to Scale)

GNDD

XCTL1

XCTL0

SYNC3

SYNC2

SYNC1

GNDD

VDD

RESET

PWRDWN

VDD

PDMNFT

GNDA

HPOUTL

HPOUTC

HPOUTR

VCC

SUML

SUMR

VCC

VDD

VCC

SDO

SDFS

GNDD

TSI

TSO

GNDD

VDD

AUX3R

AUX3L

AUX2R

AUX2L

AUX1R

AUX1L

MICR

MICL

MIN

PIN DESCRIPTION

Serial Interface

Pin Name

PQFP

TQFP

I/O

Description

SCLK

I/O

Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output

to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock

as an input when the BM pin is driven LO. When the AD1843 is configured in

master mode, the SCLK frequency may be set to either 12.288 MHz or 16.384 MHz

with the SCF bit in Control Register Address 26.

SDFS

I/O

Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame

synchronization signal as an output to the serial bus when the Bus Master (BM)

pin is driven HI and accepts the frame synchronization signal as an input when

the BM pin is driven LO.

SDI

100

Serial Data Input. SDI is used by peripheral devices such as the host CPU or a

DSP to supply control and playback data information to the AD1843. All control

and playback transfers are 16 bits long, MSB first.

SDO

Serial Data Output. SDO is used to supply status/control register readback and

capture data information to peripheral devices such as the host CPU or a DSP.

All status/control register readback and capture data transfers are 16 bits long,

MSB first. A three-state output driver is used on this pin.

Bus Master. When BM is tied HI the AD1843 is the serial bus master. The

AD1843 will then supply the serial clock (SCLK) and the frame sync (SDFS)

signals for the serial bus. No more than one device (AD1843/CPU/DSP) should

be configured as the serial bus master. When BM is tied LO, the AD1843 is con-

figured as a bus slave, and will accept the SCLK and SDFS signals as inputs. The

logic level on this pin must not be changed once RESET is deasserted (driven HI).

AD1843JS Datasheet(PDF) 7 Page - Analog Devices

AD1843JS Datasheet(HTML) 7 Page - Analog Devices

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