AD1843JS datasheet(20/64 Pages) AD

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AD1843

for Control Register write data input and read data output. The

remaining slots are used for playback (DAC) data input and

capture (ADC) data output, where each channel has an assigned

slot. Table II and Figure 11 illustrate these slot assignments.

Since the conversion channels of the AD1843 can be pro-

grammed to run at different sample rates, a communication

mechanism indicates when playback channels request data,

when playback data is actually sent to the AD1843, and when

transmission of capture data from the AD1843 becomes neces-

sary. This is facilitated by the Control and Status Words lo-

cated in the first slot. The Control Word indicates which slots

in the current frame contain valid playback data. The Status

Word indicates if playback data can be sent to the AD1843 dur-

ing the next frame, and which slots in the current frame contain

valid capture data. See the descriptions of the Control Word

and the Status Word below for additional detail.

Four word FIFO buffers are used on the inputs of each of the

DACs to allow data to be transferred in small bursts. This re-

duces the required response time to playback data requests, and

also buffers differences between the frame sync rate and the

channel sample rate. The Status Word indicates that playback

data can be sent if there is any room in the buffers, thus tending

to keep the input buffers full. Underrun flags are available in

Control Register 1, which indicate if an input buffer ran out of

data. If an underrun occurs, a zero is used in place of the un-

available data. To ensure underruns do not occur, playback data

must be sent to the AD1843 within two sample periods after the

status word indicates that the DAC FIFO is not full.

Note that the DAC Not Full status bits (DA2RQ and DA1RQ

in the Status Word Output) are updated immediately (i.e., in

the same frame as a valid write to the DAC FIFOs). If the DAC

Input Valid Flags (DA2V and DA1V in the Control Word

Input) are set (i.e., DAC data is valid) and only one location in

the DAC1 and DAC2 input FIFOs is available, then the

DA2RQ and DA1RQ status bits will reflect this valid write, and

will be reset to “0.” This is possible because the DA2V and

DA1V bits are in the most significant bits of the Control Word

and the DA2RQ and DA1RQ bits are in the least significant bits

of the Status Word, and the AD1843 uses this intervening time

Table II. AD1843 Slot Assignment

32 Slot Mode (FRS Reset to “0”)

Slot

SDI Pin

SDO Pin

0 & 16

Control Word Input

Status Word Output

1 & 17

Control Register Data Input

Control Register Data Output

2 & 18

Playback Data Input—DAC1 Left

Capture Data Output—ADC Left

3 & 19

Playback Data Input—DAC1 Right

Capture Data Output—ADC Right

4 & 20

Playback Data Input—DAC2 Left

Reserved (Unused)

5 & 21

Playback Data Input—DAC2 Right

Reserved (Unused)

16 Slot Mode (FRS Set to “1”)

Slot

SDI Pin

SDO Pin

Control Word Input

Status Word Output

Control Register Data Input

Control Register Data Output

Playback Data Input—DAC1 Left

Capture Data Output—ADC Left

Playback Data Input—DAC1 Right

Capture Data Output—ADC Right

Playback Data Input—DAC2 Left

Reserved (Unused)

Playback Data Input—DAC2 Right

Reserved (Unused)

produced by an AD1843 serving as bus master, an AD1843

serving as bus slave does not actually require these frame sizes.

When FRS is set to “1,” a slave will operate correctly with any

number or fraction of slots, provided there are enough slots for

it to complete its necessary communication (see below). When

FRS is reset to “0,” a slave can also operate correctly with a

wide range in the number of slots per frame, however it will au-

tomatically retake ownership of the serial interface bus 16 slots

after it is first given ownership of the bus in a frame.

The nominal minimum number of slots when the AD1843 is

configured in slave mode is six. The codec must be supplied

with at least 6

× 16 = 96 SCLK periods (both rising and falling

edges); SCLK may be gated (i.e., no need to be continuous)

between valid slots.

While SDFS marks the beginning of frames, AD1843 bus own-

ership during a frame is controlled by the TSI (Time Slot In)

and TSO (Time Slot Out) pins. When bus slave, a level HI on

TSI grants the AD1843 bus ownership beginning with the next

SCLK period. The TSI pin is monitored only when an AD1843

does not already own the bus; once an AD1843 is given owner-

ship of the bus, the level on TSI is ignored until one SCLK

period before bus ownership is relinquished. Bus ownership will

last for six slots. Coincident with the final SCLK period of the

final slot owned, the AD1843 asserts TSO HI. This allows

chaining of AD1843s onto a common serial bus by connecting

the TSO pin of one AD1843 to the TSI pin on the next later

AD1843 in a chain. In single codec systems where the

SoundComm is configured as bus slave, connect the AD1843

SDFS and TSI signals together. When an AD1843 is bus mas-

ter, its function is identical to that just described for the slave,

except a bus master always owns the first six slots and its TSI

pin is ignored (but should be tied LO).

Whenever an AD1843 does not own the bus, its SDO pin will

be three-stated and its SDI pin is ignored. Figures 7 through 10

illustrate the signal, slot, sample and frame relationships for the

four basic operating modes of the AD1843 serial interface.

The AD1843 requires slots of communication each time it takes

ownership of the serial bus. The first slot is used for a Control

Word input and a Status Word output. The second slot is used

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