AD1843JS datasheet(28/64 Pages) AD

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REV. 0

–28–

AD1843

Address 0

Codec Status and Revision Identification

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

INIT

PDNO

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

ID3

ID2

ID1

ID0

This register is read only.

INIT

Clock Initialization Flag. This bit is set to “1” if the AD1843’s internal clocks generated from the crystal input pin

XTALI have not yet stabilized. When set to “1,” Control Registers may be read if the AD1843 is configured as a Bus

Slave (see the definition for the BM pin), but Control Register writes will be blocked. This bit is set to a “1” after the

RESET

pin is asserted, or when the power-down sequence (initiated by asserting the PWRDWN pin) has completed.

The bit is reset to “0” usually within 400 to 800

µsec after the RESET or the PWRDWN pin is deasserted, depending

upon parasitic capacitance on the XTALI and XTALO pins outside the AD1843. Because these parasitics are a func-

tion of the board design and layout, the exact amount of time required for the crystal to start to oscillate, and the in-

ternal clocks to stabilize cannot be known exactly in advance.

PDNO

Converter Power-Down Flag. This bit is set to “1” if the AD1843 conversion resources are powered down, or are in

the process of entering or exiting power down. Conversion resources are all resources in the AD1843 with the excep-

tion of the three clock generators and the serial interface. Conversion power-down is entered if either the power-down

pin (PWRDWN) is driven LO, or if the PDNI (Converter Power Down) bit in Control Register Address 28 is as-

serted. Power down is exited only if both pin (PWRDWN) and bit (PDNI) are deasserted. When this bit is set to

“1,” Control Registers may still be read, but only Control Registers 16–24, 26 and 28 which do not manage conver-

sion resources may be written. See the “Power Management” section for further details. This bit is set to “1” imme-

diately after a reset since the PDNI bit is initially asserted after a reset.

ID3:0

Revision Identification. These bits define the revision level of the AD1843. The first version of the AD1843 is

“0001.”

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1100 0000 0000 0001 (C001 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

Address 1

Channel Status Flags

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

SU2

SU1

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

OVR1

OVR0

OVL1

OVL0

This register is cleared to all “0” after any read or write access.

SU2

DAC2 Sample Underrun. When set to “1,” this bit indicates that the four word stereo input buffer for DAC pair 2

ran out of samples. If this occurs, zeros are used in place of the unavailable data. This bit is “sticky” and is cleared

after any write to this register. It is also cleared by powering down DAC2 (see the DA2EN bit in Control Register

Address 27).

SU1

DAC1 Sample Underrun. When set to “1,” this bit indicates that the four word stereo input buffer for DAC pair 1

ran out of samples. If this occurs, zeros are used in place of the unavailable data. This bit is “sticky” and is cleared

after any write to this register. It is also cleared by powering down DAC1 (see the DA1EN bit in Control Register

Address 27).

OVR1:0

ADC Right Overrange Detect. These bits record the largest output magnitude on the ADC right channel and are

cleared to “00” after any write to this register. The peak amplitude as recorded by these bits is “sticky,” i.e., the larg-

est output magnitude recorded by these bits will persist until these bits are explicitly cleared. They are also cleared by

powering down the ADC right channel (see the ADREN bit in Control Register Address 27).

00 = Greater than –1.0 dB underrange

01 = Between –1.0 dB and 0 dB underrange

10 = Between 0 dB and 1 dB overrange

11 = Greater than 1.0 dB overrange

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