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AD1843JS Datasheet(PDF) 8 Page - Analog Devices

Part # AD1843JS
Description  Serial-Port 16-Bit SoundComm Codec
PDF  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1843JS Datasheet(HTML) 8 Page - Analog Devices

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AD1843
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AD1843
TOP VIEW
(Not to Scale)
GNDD
XCTL1
NC
XCTL0
SYNC3
SYNC2
SYNC1
NC
GNDD
VDD
RESET
PWRDWN
NC
VDD
PDMNFT
NC
GNDA
HPOUTL
HPOUTC
HPOUTR
VCC
SUML
SUMR
NC
VCC
NC
VDD
VCC
NC
NC
NC
NC
SDO
SDFS
GNDD
TSI
TSO
GNDD
VDD
CS
BM
AUX3R
AUX3L
AUX2R
AUX2L
AUX1R
AUX1L
MICL
MICR
MIN
NC = NO CONNECT
Serial Interface (Continued)
Pin Name
PQFP
TQFP
I/O
Description
CS
9
11
I
Chip Select. When CS is set HI, the serial interface I/O pins will be in their normal
active states. When CS is reset LO, SCLK, SDFS, and SDO are three-
stated; SCLK, SDFS and SDI inputs are ignored; and TSO drives out the logic
level received on TSI.
TSO
6
7
O
Time Slot Output. TSO is asserted HI by the AD1843 simultaneously with the LSB
of the last time slot used by the AD1843. It is used to daisy-chain multiple AD1843s
on a common TDM serial bus. If the power-down (PWRDWN) pin is asserted or if
the chip select pin (CS) is deasserted, TSO is set to the logic level on the TSI pin,
allowing powered-down or unselected AD1843s on a daisy-chain to be skipped.
TSI
5
6
I
Time Slot Input. Asserting TSI HI indicates to the AD1843 that it should use
the next six time slots beginning on the next SCLK period. It also enables TSO
to be asserted at the end of these six time slots. TSI is ignored (but should be tied
LO) when the AD1843 is the bus master since the bus master uses the first time
slots in a TDM frame.
XCTL[1:0]
59, 58
72, 74
I/O
External Control. These signals reflect the status of bits (Data 8 and 9) in Control
Register Address 28 of the AD1843. They may be used for signaling or controlling
external logic.
PIN CONFIGURATIONS
100-Lead TQFP



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