AD1843JS datasheet(33/64 Pages) AD

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AD1843

REV. 0

–33–

MNM4:0

Left and Right Mono Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB.

00000 = +12.0 dB Gain

01000 = 0.0 dB

11111 = –34.5 dB Attenuation

ALLMM

All Mix Mute. Mutes all mixing (MIC, AUX1, AUX2, AUX3, and DAC2) to left and right DAC1, overriding the

independent mute control bits in Control Register Addresses 3 through 8.

0 = Mix to DAC1 Enabled

1 = Mix to DAC1 Muted

MNOM

Mono Output Mute

0 = Mono Output Enabled

1 = Mono Output Muted

HPOM

Headphone Output Mute (Left and Right)

0 = Headphone Output Enabled

1 = Headphone Output Muted

HPOS

Headphone Output Voltage Swing (Left and Right)

0 = 2 volts peak-to-peak

1 = 4 volts peak-to-peak

SUMM

Sum Left and Right Mute. Mutes mixing from SUML and SUMR pins to DAC1.

0 = SUML and SUMR Mix to DAC1 Enabled

1 = SUML and SUMR Mix to DAC1 Muted

DAC2T

DAC2 Gain/Attenuation Change Timing. This bit controls when changes to the DAC2 gain/attenuation setting

(Control Register 10) take effect. When set to “1,” changes take effect immediately. When reset to “0,” changes are

delayed until either the output level on DAC2 crosses zero (midscale), or until after a 10 to 12 ms time-out period is

reached. Delaying gain/attenuation changes until zero crossings reduces instantaneous output voltage changes, which

reduces audible “clicks.”

0 = Gain/Attenuation Changes Applied on Signal Zero Crossing or After a 10-12 ms Time-Out

1 = Gain/Attenuation Changes Applied Immediately

DAC1T

DAC1 Gain/Attenuation Change Timing. This bit controls when changes to the DAC1 gain/attenuation setting

(Control Register 9) take effect. When set to “1,” changes take effect immediately. When reset to “0,” changes are

delayed until either the output level on DAC1 crosses zero (midscale), or until after a 10 to 12 ms time-out period is

reached. Delaying gain/attenuation changes until zero crossings reduces instantaneous output voltage changes, which

reduces audible “clicks.”

0 = Gain/Attenuation Changes Applied on Signal Zero Crossing or After a 10-12 ms Time-Out

1 = Gain/Attenuation Changes Applied Immediately

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1000 1000 0110 1000 (8868 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions powered down). The MSB half (Data 15 through Data 8) of this Control Reg-

ister is cleared to default and cannot be written to also when: the AAMEN bit (analog input to analog mix disabled),

or the ANAEN bit (analog channels powered down) in Control Register 27 is reset to “0.”

Address 9

Output Control—DAC1 Analog Gain/Attenuation

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LDA1GM

res

LDA1G5

LDA1G4

LDA1G3

LDA1G2

LDA1G1

LDA1G0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RDA1GM

res

RDA1G5

RDA1G4

RDA1G3

RDA1G2

RDA1G1

RDA1G0

LDA1GM

Left DAC1 Analog Mute

0 = Left DAC1 Enabled

1 = Left DAC1 Muted

AD1843JS Datasheet(PDF) 33 Page - Analog Devices

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