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AD1843

When in Video Lock Mode (C3REF and C3VID are both set to “1”):

Bits C3M7:0 select the Conversion clock rate. The most significant bit (C3M7) must be set to indicate the type of

video lock, either NTSC or PAL. For an NTSC lock, C3M7 must be reset to “0,” and the SYNC3 pin must

receive the NTSC sync frequency (525 lines/frame

× 30 Hz × 1000/1001 frame rate ≈ 15.734 kHz). For a PAL lock,

C3M7 must be set to “1,” and the SYNC3 pin must receive the PAL sync frequency (625 lines/frame

× 25 Hz frame

rate

≈ 15.625 kHz). The next three most significant bits (C3M6:4) select a desired base Conversion clock rate, and

the least significant four bits (C3M3:0) select a divisor. The Conversion clock created by Clock Generator 3 will be

the base divided by the divisor. The following tables list the possible choices for base and divisor.

NTSC

(C3M7 = “0”):

Base Frequency In Hz (C3M6:4)

48,000

32,000

44,100

× 2/3

48,000*

44,056

Divisor

(C3M3:0)

(000)

(001)

(010)

(011)

(100)

(101)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

*When C3M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.570 kHz.

PAL

(C3M7 = “1”):

Base Frequency In Hz (C3M6:4)

48,000

32,000

44,100

× 2/3

Divisor

(C3M3:0)

(000)

(001)

(010)

(011)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

Address 23

Clock Generator 3 Control—Sample Rate

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

C3C15

C3C14

C3C13

C3C12

C3C11

C3C10

C3C9

C3C8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

C3C7

C3C6

C3C5

C3C4

C3C3

C3C2

C3C1

C3C0

C3C15:0

Clock Generator 3 Conversion (Sample) Rate Select. Defines the conversion rate produced by Clock Generator 3

when not referenced to the SYNC3 pin (Control Register Address 22 Bit 15 [C3REF]). One LSB represents exactly

one Hertz, assuming a 24.576 MHz clock input on the XTALI pin. Usable range is 4 kHz (0x0FA0) to 54 kHz

(0xD2F0).

Initial default state after reset: 1011 1011 1000 0000 (BB80 hex), which is 48 kHz, assuming a 24.576 MHz clock in-

put on the XTALI pin. Cleared to default and cannot be written to when: the RESET pin is asserted LO; or when

the PWRDWN pin is asserted LO.

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