AD1843JS datasheet(45/64 Pages) AD

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AD1843

REV. 0

–45–

Address 24

Clock Generator 3 Control—Sample Phase Shift

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

C3PD

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

C3P7

C3P6

C3P5

C3P4

C3P3

C3P2

C3P1

C3P0

C3PD

Clock Generator 3 Phase Shift Direction. This bit controls the direction of sample clock phase shift.

0 = Phase Advance

1 = Phase Retard

C3P7:0

Clock Generator 3 Phase Shift Magnitude. These bits control the magnitude of sample clock phase shift. One LSB

represents exactly 0.12 degrees. LSBs are processed and decremented at a rate of 3.072 MHz (assuming a 24.576

MHz clock input on the XTALI pin). When this register is read, it indicates any phase advance/retard remaining to

be processed as of the beginning of slot 0 if bus master, or when TSI was received if bus slave. This register may be

overwritten even if all previously programmed phase advance/retard has not been processed. When written, the con-

tents of this register (just prior to the write) are transmitted during slot 1 of the following frame (as with all Control

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the G3EN bit in Control Register

Address 28 is reset to “0” (clock generator 3 disabled).

Address 25

Codec Configuration—Digital Filter and Mode Select

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DRSFLT

DAMIX

res

DA2FLT

DA1FLT

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DAADR1

DAADR0

DAADL1

DAADL0

res

ADRFLT

ADLFLT

Restrictions: Modem filter should not be selected when channel sample rate is above 24 kHz.

DRSFLT

Digital Resampler Filter Mode. DAC2 is sacrificed so that the remaining four channels (left ADC, right ADC, left

and right DAC1) have sufficient resources to realize the more stringent resampling filter requirements. See below for

filter specifications. (Note: Digital resampling can be done without using the resampling filters but performance is not

as optimal.) This bit can be altered only if all channels (DAC1, DAC2, ADL, and ADR) are powered down. Note

that this bit enables the digital resampler filters, but does not enable the digital resampler data pathways. Use the

DAADR1:0 and DAADL1:0 bits to enable the resampler data pathways.

0 = Audio/Modem Filter Modes (Defined by DA1FLT, DA2FLT, ADLFLT and ADRFLT)

1 = Digital Resampler Filter Mode (DA1FLT, DA2FLT, ADLFLT and ADRFLT filter selections are ignored).

DAMIX

DAC Digital Mix Enable. When set to “1,” DAC1 and DAC2 are mixed at the output of the digital interpolation fil-

ter. Left and right channels are still separated, but DAC1 and DAC2 outputs are identical. This bit can be altered

only if both DAC1 and DAC2 are powered down.

0 = Digital Mix Disabled

1 = Digital Mix Enabled

DA2FLT

DAC2 (Left and Right Channels) Digital Filter Select and Analog Output Swing Select. Digital filter selected is over-

ridden when DRSFLT is set to “1.” See below for filter specifications. This bit can be altered only if DAC2

is powered down.

0 = Digital Audio Filter. Nominal analog swing is 2.000 V p-p when output level is +0.0 dB (see Control Register

Address 10).

1 = Digital Modem Filter. Nominal analog swing is 3.156 V p-p when output level is +4.5 dB (see Control Register

Address 10).

AD1843JS Datasheet(PDF) 45 Page - Analog Devices

AD1843JS Datasheet(HTML) 45 Page - Analog Devices

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