AD1843JS datasheet(37/64 Pages) AD

37 / 64 page

AD1843

REV. 0

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Address 15

Codec Configuration—Channel Sample Rate Source Select

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

DA2C1

DA2C0

DA1C1

DA1C0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

ADRC1

ADRC0

ADLC1

ADLC0

DA2C1:0

DAC2 Sample Rate Source. Selects the sample rate clock source for left and right channels of DAC2.

00 = Conversion Sample Rate is 48.0 kHz

01 = Conversion Sample Rate is from Clock Generator 1

10 = Conversion Sample Rate is from Clock Generator 2

11 = Conversion Sample Rate is from Clock Generator 3

DA1C1:0

DAC1 Sample Rate Source. Selects the sample rate clock source for left and right channels of DAC1.

00 = Conversion Sample Rate is 48.0 kHz

01 = Conversion Sample Rate is from Clock Generator 1

10 = Conversion Sample Rate is from Clock Generator 2

11 = Conversion Sample Rate is from Clock Generator 3

ADRC1:0

ADC Right Sample Rate Source. Selects the sample rate clock source for the right ADC channel.

00 = Conversion Sample Rate is 48.0 kHz

01 = Conversion Sample Rate is from Clock Generator 1

01 = Conversion Sample Rate is from Clock Generator 2

11 = Conversion Sample Rate is from Clock Generator 3

ADLC1:0

ADC Left Sample Rate Source. Selects the sample rate clock source for the left ADC channel.

00 = Conversion Sample Rate is 48.0 kHz

01 = Conversion Sample Rate is from Clock Generator 1

10 = Conversion Sample Rate is from Clock Generator 2

11 = Conversion Sample Rate is from Clock Generator 3

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled).

Address 16

Clock Generator 1 Control—Mode

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

C1REF

C1VID

C1PLLG

C1P200

C1X8/7

C1C128

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

C1M7

C1M6

C1M5

C1M4

C1M3

C1M2

C1M1

C1M0

C1REF

Clock Generator 1 Reference Select. Selects the fundamental clock reference used by Clock Generator 1 to

synthesize its “Conversion” (sample) and “Bit” clock rates.

0 = Clocks are referenced to the input on pin XTALI (crystal or master clock input).

Sample clock frequency is defined by Control Register Address 17 and Bit C1X8/7.

Sample clock phase may be shifted by Control Register Address 18.

Bit clock frequency is defined by bits C1M7:0 and C1P200.

Bit C1VID is ignored.

1 = Clocks are referenced to the input on pin SYNC1 (Sync 1 Clock Input).

Sample clock frequency is defined by C1VID and C1M7:0.

Sample clock phase is locked to SYNC1 and cannot be shifted.

Bit clock frequency is defined by bits C1M7:0 and C1P200 unless in Video Lock Mode (C1VID set to “1”)

where the Bit clocks are not produced.

Control Register Addresses 17, 18 and the C1X8/7 bit are ignored.

AD1843JS Datasheet(PDF) 37 Page - Analog Devices

AD1843JS Datasheet(HTML) 37 Page - Analog Devices

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