AD1843JS datasheet(36/64 Pages) AD

36 / 64 page

REV. 0

–36–

AD1843

Address 13

Digital Mix Control—ADC to DAC1

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LAD1MM

res

LAD1M5

LAD1M4

LAD1M3

LAD1M2

LAD1M1

LAD1M0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RAD1MM

res

RAD1M5

RAD1M4

RAD1M3

RAD1M2

RAD1M1

RAD1M0

Restrictions: ADC and DAC channel mixed must receive conversion rate from same Clock Generator. Serial interface must be run-

ning at a rate greater than or equal to the ADC/DAC conversion rate. For bus master: SDFS frequency

≥ ADC/DAC conversion rate. For

bus slave: TSI frequency

≥ ADC/DAC conversion rate.

LAD1MM

Digital Mix of Left ADC Output with Left DAC1 Input Mute.

0 = Mix Enabled

1 = Mix Muted

LAD1M5:0

Digital Mix of Left ADC Output with Left DAC1 Input Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111110 = –93.0 dB Attenuation

111111 = Full Mute

RAD1MM

Digital Mix of Right ADC Output with Right DAC1 Input Mute.

0 = Mix Enabled

1 = Mix Muted

RAD1M5:0

Digital Mix of Right ADC Output with Right DAC1 Input Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111110 = –93.0 dB Attenuation

111111 = Full Mute

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1000 0000 1000 0000 (8080 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled).

Address 14

Digital Mix Control—ADC to DAC2

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LAD2MM

res

LAD2M5

LAD2M4

LAD2M3

LAD2M2

LAD2M1

LAD2M0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RAD2MM

res

RAD2M5

RAD2M4

RAD2M3

RAD2M2

RAD2M1

RAD2M0

Restrictions: ADC and DAC channel mixed must receive conversion rate from same Clock Generator. Serial interface must be run-

ning at a rate greater than or equal to the ADC/DAC conversion rate. For bus master: SDFS frequency

≥ ADC/DAC conversion rate. For

bus slave: TSI frequency

≥ ADC/DAC conversion rate.

LAD2MM

Digital Mix of Left ADC Output with Left DAC2 Input Mute.

0 = Mix Enabled

1 = Mix Muted

LAD2M5:0

Digital Mix of Left ADC Output with Left DAC2 Input Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111110 = –93.0 dB Attenuation

111111 = Full Mute

RAD2MM

Digital Mix of Right ADC Output with Right DAC2 Input Mute.

0 = Mix Enabled

1 = Mix Muted

RAD2M5:0

Digital Mix of Right ADC Output with Right DAC2 Input Attenuation Select. Least significant bit represents –1.5 dB.

000000 = +0.0 dB Attenuation

111110 = –93.0 dB Attenuation

111111 = Full Mute

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1000 0000 1000 0000 (8080 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled).

AD1843JS Datasheet(PDF) 36 Page - Analog Devices

AD1843JS Datasheet(HTML) 36 Page - Analog Devices

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