CSP1027 datasheet(16/64 Pages) AGERE

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CSP1027 Voice Band Codec for

Data Sheet

Cellular Handset and Modem Applications

December 1999

Lucent Technologies Inc.

4 Architectural Information (continued)

4.5 Clock Generation

Figure 17 on page 15 shows the clock generation and

distribution for the CSP1027. The programmable divid-

ers can customize the codec sample and master clock

rates for a variety of applications in addition to standard

8 kHz sampling, while allowing a range of values for

the crystal-controlled input clock. In Figure 17 on page

15, XOSCEN is a chip input to enable the crystal oscil-

lator circuit. XLO and XHI are the two leads for the

crystal. CLK is the chip clock input if the crystal is not

used. CKS is the internal codec sample clock, typically

8 kHz. CKOS is the internal codec oversampled clock,

typically 1 MHz. CKO1 and CKO2 are general-purpose

clocks brought out to chip pins. CDIV1 and CDIV2 are

programmable dividers with a range from 1 to 31.

CDIV0 is programmed to be 1 or 2, but extra clock

pulses can be added or subtracted at the output for one

period of time following a write to the control register

cioc1. This one-time increase or decrease in the num-

ber of clocks is programmed by ADJMOD and ADJ and

causes a phase shift in the CKO1 and CKS output. F1

is an integral or a fractional divider controlled by the

five programmable coefficients shown connected to it.

With the fractional divide, the period of CKOS will vary,

but the period of CKS will be constant.

The following discussion begins with the crystal oscilla-

tor and is followed by a detailed description of each

divisor block. Section 7.5 on page 45 provides some

examples of how to program the clocks.

4.5.1 Crystal Oscillator

The CSP1027 has a selectable on-chip clock oscillator.

A logic 1 on the XOSCEN pin enables the crystal oscil-

lator. A logic 0 disables the oscillator, powers it down,

and selects the input buffer connected to the CLK pin.

To use the oscillator, select a 20 MHz to 30 MHz funda-

mental-mode crystal with a series resistance less than

Ω and a mutual capacitance less than 7.0 pF. Con-

nect the crystal between the XLO and XHI pins, and

add 10 pF capacitors between XLO and ground, and

XHI and ground. The XOSCEN pin enables and dis-

ables the crystal oscillator. See the application informa-

tion on optimizing the oscillator performance.

4.5.2 Clock Divider 2

Figure 18. Clock Divider 2

The CDIV2 field in cioc0 (see Table 7 on page 26) sets

the clock divider that generates the output clock,

CKO2. The clock output is a general-purpose clock that

can be used to clock external logic or processors.

CDIV2 ranges from 1 to 31, with 0 holding the output

low. RSTB going low sets CDIV2 to ÷16. CKO2 is

active while RSTB is low and synchronized by RSTB

going high.

4.5.3 Clock Divider 0

Figure 19. Clock Divider 0

The CDIV0 field in cioc1 (see Table 8 on page 27) sets

the clock divider that generates the internal clock 0

(ICLK0) to either divide by one or divide by two. The

ADJMOD and ADJ fields in cioc1 are used to adjust

the phase of ICLK0 by increasing or decreasing the

rate of ICLK0 for a burst of pulses, one time only. This

event occurs each time control register cioc1 is written

with nonzero values of ADJ. For example, let CDIV0 be

set to ÷2, ADJ to seven, and ADJMOD to one

(advance). After this word is written to the cioc1 regis-

ter, seven ICLK0 pulses will occur at the same rate as

ICLK, not divided by two. These seven clock pulses

shift the phase of CKOS, CKS, and CKO1 earlier, thus

advancing these clocks. If ADJMOD is set to zero

(retard), the ÷2 becomes a ÷3 for seven pulses of

ICLK0. The CDIV0 clock divider is temporarily changed

internally so that it divides by one greater, to retard the

clocks, or one less, to advance the clocks, for the spec-

ified number of ICLK0 cycles. Note that the CDIV0

clock divider must be set to divide by two in order to

advance and retard the clocks. If CDIV0 clock divider is

set to divide by 1, one can only retard the clocks.

÷CDIV2

ICLK

CKO2

5-7589 (F)

÷CDIV0

ICLK

ICLK0

ADJMOD,

ADJ

5-7588 (F)

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