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CSP1027 Datasheet(PDF) 45 Page - Agere Systems

Part # CSP1027
Description  CSP1027 Voice Band Codec for Cellular Handset and Modem Applications
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Manufacturer  AGERE [Agere Systems]
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CSP1027 Datasheet(HTML) 45 Page - Agere Systems

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Lucent Technologies Inc.
Data Sheet
CSP1027 Voice Band Codec for
December 1999
Cellular Handset and Modem Applications
45
7 Application Information (continued)
Thus, the contributions to frequency variation add up
as follows:
Initial Tolerance of Crystal
10.0 ppm
Temperature Tolerance of Crystal
25.0 ppm
Aging Tolerance of Crystal
6.0 ppm
Load Capacitor Variation
4.7 ppm
CSP1027 Circuit Variation
15.5 ppm
C0 Variation
7.8 ppm
Board Variation
23.3 ppm
Total
92.3 ppm
This type of detailed analysis should be performed for
any crystal-based application where frequency accu-
racy is critical.
7.5 Programmable Clock Generation
Refer to Figure 17 on page 15 for the following discus-
sion.
The programmable clock divider is set by writing the
6-bit CDIV3 field of the cioc2 register (see Table 9 on
page 28). The user can select an appropriate integer
value which sets the ratio of the CLK input clock to the
oversampling rate of the codec. The following examples
illustrate this feature.
7.5.1 Application Example 1
s
GSM application.
s
Input clock, CLK, rate: 26 MHz (38.46 ns).
s
Codec PCM rate required: 8 kHz (oversampling
rate = 1 MHz).
Solution:
s
CLK/CKOS = 26, so set CLK/ICLK0 = 1 and ICLK0/
CKOS to 26.
s
Set CDIV0 = 0 and CDIV3 = 26 (011010).
7.5.2 Application Example 2
s
IS-54 application.
s
Input clock, CLK, rate: 40 MHz (25.0 ns).
s
Codec PCM rate required: 8 kHz (oversampling
rate = 1 MHz).
Solution:
s
CLK/CKOS = 40, so set CLK/ICLK0 = 1 and ICLK0/
CKOS to 40.
s
Set CDIV0 = 0 and CDIV3 = 40 (101000).
7.5.3 Application Example 3
s
Modem data pump.
s
Codec sampling frequency required = 9.6 kHz
(instead of 8 kHz).
s
Need highest possible input clock, CLK, rate (allow-
able by the DSP).
Solution:
s
Codec oversampling rate = 9.6 kHz * 125 = 1.2 MHz.
s
Assuming a DSP16A or DSP1616 with
maximum rate of 40 MHz,
CLK = 39.6 MHz = 1.2 MHz x 33, so
CLK/ICLK0 = 1 and ICLK0/CKOS = 33.
s
Set CDIV0 = 0 and CDIV3 = 33 (100001).
s
Disable the high-pass filters (HPFE = 1) because the
–3 dB corner frequency is now too high
(270 Hz x 1.2 = 324 Hz).
s
Low-pass filter –3 dB corner frequency is now
4.08 kHz (= 3.4 kHz x 1.2). (Note that external DSP
software can provide additional postfiltering, if
desired.)



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