CSP1027 datasheet(17/64 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

CSP1027 Voice Band Codec for

December 1999

Cellular Handset and Modem Applications

4 Architectural Information (continued)

CDIV0 has values of 1 or 2, ADJMOD is 0 or 1, and

ADJMOD ranges from 1 to 127, with 0 selecting no

clock adjust. RSTB going low sets CDIV0 to ÷2. ICLK0

is active while RSTB is low and synchronized by RSTB

going high.

4.5.4 Clock Divider 1

Figure 20. Clock Divider 1

The CDIV1 field in cioc1 (see Table 8 on page 27) sets

a clock divider that generates the CKO1 output clock.

This general-purpose clock output can be used for

clocking another codec in the system, such as the

CSP1084. The ability to phase adjust the output clock

and the codec sampling clock simultaneously is an

important feature. CDIV1 ranges from 1 to 31, with 0

disabling the output. RSTB going low sets CDIV1

to ÷16. CKO1 is active while RSTB is low and synchro-

nized by RSTB going high.

4.5.5 Sampling Clocks Generation

Figure 21. Sampling Clocks Generation

The oversampling codec clock CKOS, typically 1 MHz,

is used in the front sections of the A/D and the back

sections of the D/A. The lower-frequency codec clock,

CKS, typically 8 kHz, is the sample clock at the output

of the A/D and the input to the D/A. The sampling clock

frequency, fS, is the oversampling clock frequency, fOS,

divided by 125 (the fixed oversampling ratio). The

divide by 125 must remain fixed, since it is constrained

by the architecture of the codec digital filters. Many sys-

tems, however, have fixed high-frequency clocks and

fixed sampling clocks, so it is necessary to have a great

deal of flexibility in the creation of the codec clock CKS.

The CSP1027 solves this problem in a unique way, by

providing a programmable, fractional divider, F1.

F1 is the programmable ratio between ICLK0 and

CKOS. The equation for F1 is:

where 3

≤ M ≤ 64, 0 ≤ N ≤ 62, and S = {1, –1};

or M = 2, 0

≤ N ≤ 62, and S = 1;

or M = 1, N = 0, and S = 1.

M is encoded by CDIV3 (see Table 3 on page 18), N is

encoded by CDIF0, CDIF1, and CDIF2 (see Table 5 on

page 19), and S is encoded by CDIFS (see Table 4 on

page 18).

CKS is generated by dividing CKOS by 125. The fre-

quency of CKS can be described by:

Note that when N = 0, ICLK0 is simply divided by the

integer M to create the oversampling clock, CKOS. This

is the preferred method for generating the sampling

clock. If N

≠ 0, the fractional division results in an over-

sampling clock, CKOS, whose period varies with time

such that the average period is the desired fraction.

This variation in the oversampling clock period is mini-

mized by the clock generator but can cause distortion

in the codec. Because the denominator of the fraction

is fixed at 125, the period of the sampling clock, CKS,

will be an integer multiple of the period of the internal

clock, ICLK0, and will not vary. This is more clearly

shown by the following equation:

The expanded equation below explains what is hap-

pening in the time domain:

During each sampling period,

, there are (125 – N)

oversampling clock cycles of period

and N

oversampling clock cycles of period

. The N

oversampling clock cycles are evenly distributed

among the (125 – N) oversampling clock cycles to min-

imize the distortion due to oversampling clock cycles of

differing period. The values for CDIF[0—2] in Table 5

on page 19 have been selected to achieve the even

distribution.

÷CDIV1

ICLK0

CKO1

5-7587 (F)

÷F1

ICLK0

CKS

÷125

CKOS

CDIFS, CDIF0, DSIF1,

CDIF2, CDIV3

5-7586 (F)

125

----------





fOS

125

fICLK0

125

----------





125

fICLK0

----------------

125

()

-----

125

–

()

fICLK0

----------------

()

fICLK0

--------------------

-----

fICLK0

----------------

()

fICLK0

--------------------

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