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WM8903 Datasheet(PDF) 142 Page - Wolfson Microelectronics plc |
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WM8903 Datasheet(HTML) 142 Page - Wolfson Microelectronics plc |
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142 / 178 page ![]() WM8903 Production Data w PD, Rev 4.5, June 2012 142 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10000 = Reserved 10001 = CLK_SYS / 30 10010 = CLK_SYS / 32 10011 = CLK_SYS / 44 10100 = CLK_SYS / 48 Register 1Ah Audio Interface 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R27 (1Bh) Audio Interface 3 10:0 LRCLK_RATE [10:0] 000_0010_0010 LRC Rate (Master Mode) LRC clock output = BCLK / LRCLK_RATE Integer (LSB = 1) Valid range: 8 to 2047 50:50 LRCLK duty cycle is only guaranteed with even values (8, 10, … 2046). Register 1Bh Audio Interface 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R30 (1Eh) DAC Digital Volume Left 8 DACVU 0 DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously (Write-Only Register) 7:0 DACL_VOL [7:0] 1100_0000 Left DAC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB … (0.375dB steps) C0h to FFh = 0dB Register 1Eh DAC Digital Volume Left REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R31 (1Fh) DAC Digital Volume Right 8 DACVU 0 DAC Volume Update Writing a 1 to this bit causes left and right DAC volume to be updated simultaneously (Write-Only Register) 7:0 DACR_VOL [7:0] 1100_0000 Right DAC Digital Volume 00h = Mute 01h = -71.625dB 02h = -71.250dB … (0.375dB steps) C0h to FFh = 0dB Register 1Fh DAC Digital Volume Right |
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