WM8903 datasheet(138/178 Pages) WOLFSON

138 / 178 page

WM8903

Production Data

PD, Rev 4.5, June 2012

138

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R20 (14h)

Clock Rates

MCLKDIV2

Enables divide by 2 on MCLK

0 = CLK_SYS = MCLK

1 = CLK_SYS = MCLK / 2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R21 (15h)

Clock Rates

CLK_SRC_SEL

SYSCLK Source Select

0 = MCLK

1 = FLL output

13:10

CLK_SYS_RATE [3:0]

0011

CLK_SYS / Sample rate (fs) ratio

if CLK_SYS_MODE = 00 (256*fs related clocks)

0000 = 64*fs

0001 = 128*fs

0010 = 192*fs

0011 = 256*fs

0100 = 384*fs

0101 = 512*fs

0110 = 768*fs

0111 = 1024 *fs

1000 = 1408*fs

1001 = 1536*fs

1010 to 1111 = Reserved

if CLK_SYS_MODE = 01 (272*fs related clocks)

0000 = 68*fs

0001 = 136*fs

0010 = 204*fs

0011 = 272*fs

0100 = 408*fs

0101 = 544*fs

0110 = 816*fs

0111 = 1088 *fs

1000 = 1496*fs

1001 = 1632*fs

1010 to 1111 = Reserved

if CLK_SYS_MODE = 10 (250*fs related clocks)

0000 = 125*fs

0001 = 125*fs

0010 = 250*fs

0011 = 250*fs

0100 = 375*fs

0101 = 500*fs

0110 = 750*fs

0111 = 1000 *fs

1000 = 1000*fs

1001 = 1500*fs

1010 to 1111 = Reserved

WM8903 Datasheet(PDF) 138 Page - Wolfson Microelectronics plc

WM8903 Datasheet(HTML) 138 Page - Wolfson Microelectronics plc

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