WM8903 datasheet(159/178 Pages) WOLFSON

159 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

159

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

HPL_ENA_DLY

Enables HPL intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1

after the output signal path has been configured,

and before DC offset cancellation is scheduled.

This bit should be set with at least 20us delay after

HPL_ENA.

HPL_ENA

Enables HPL input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set as the

first step of the HPL Enable sequence.

HPR_RMV_SHORT

Removes HPR short

0 = HPR short enabled

1 = HPR short removed

For normal operation, this bit should be set as the

final step of the HPR Enable sequence.

HPR_ENA_OUTP

Enables HPR output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1

after the DC offset cancellation has been

scheduled.

HPR_ENA_DLY

Enables HPR intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1

after the output signal path has been configured,

and before DC offset cancellation is scheduled.

This bit should be set with at least 20us delay after

HPR_ENA.

HPR_ENA

Enables HPR input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set as the

first step of the HPR Enable sequence.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R94 (5Eh)

Analogue

Lineout 0

LINEOUTL_RMV_SHORT

Removes LINEOUTL short

0 = LINEOUTL short enabled

1 = LINEOUTL short removed

For normal operation, this bit should be set as

the final step of the LINEOUTL Enable

sequence.

LINEOUTL_ENA_OUTP

Enables LINEOUTL output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to

1 after the DC offset cancellation has been

scheduled.

WM8903 Datasheet(PDF) 159 Page - Wolfson Microelectronics plc

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