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WM8903 Datasheet(PDF) 160 Page - Wolfson Microelectronics plc |
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WM8903 Datasheet(HTML) 160 Page - Wolfson Microelectronics plc |
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160 / 178 page  WM8903 Production Data w PD, Rev 4.5, June 2012 160 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5 LINEOUTL_ENA_DLY 0 Enables LINEOUTL intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after LINEOUTL_ENA. 4 LINEOUTL_ENA 0 Enables LINEOUTL input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the LINEOUTL Enable sequence. 3 LINEOUTR_RMV_SHORT 0 Removes LINEOUTR short 0 = LINEOUTR short enabled 1 = LINEOUTR short removed For normal operation, this bit should be set as the final step of the LINEOUTR Enable sequence. 2 LINEOUTR_ENA_OUTP 0 Enables LINEOUTR output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 1 LINEOUTR_ENA_DLY 0 Enables LINEOUTR intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after LINEOUTR_ENA. 0 LINEOUTR_ENA 0 Enables LINEOUTR input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the LINEOUTR Enable sequence. Register 5Eh Analogue Lineout 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R98 (62h) Charge Pump 0 0 CP_ENA 0 Enable charge-pump digits 0 = disable 1 = enable Register 62h Charge Pump 0 |
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