LM4308

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SNLS225C – AUGUST 2007 – REVISED MAY 2013

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Total Supply

64

µA

Current—Enabled

18

mA

Conditions: CLK = 30MHx (8X

18

mA

mode), DC = 240MHz,

DD = 480Mbps

Worse Case Data Pattern,

7

mA

constant WRITE

Supply Current—Enabled

Master

10

µA

Bus Idle (WR* = H)

8.2

mA

Slave

>1

µA

2.9

mA

Supply Current—Disable

Master

8

µA

Power Down Modes

PD* = L, or CLK stop

9

µA

Slave

8

µA

PD* = L, or Auto

9

µA

Sleep

PD

Power Dissipation

25% Bus active

Master

15

mW

Slave

6

mW

Idle Bus

Master

14.8

mW

Slave

5.2

mW

Master

195

µW

Slave

8

µW

PD*=L

Master

>0.1

µW

Slave

>0.1

µW

(6)

For IDD measurements a checkerboard pattern 2AAAA-15555 was used.

(7)

Typical PD for QVGA application. Conditions: 1.8V, 25C, 19.2MHz CLK and 8X, 10% blanking, 1fps. Link is started up, 1 frame (240 x

320) is sent and link is powered down.

SWITCHING CHARACTERISTICS

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PARALLEL BUS TIMING See also Table 5 and Figure 9

Set Up Time

Master Input, WRITE

5

ns

Hold Time

5

ns

Rise Time

RD* and WR* Slave

7

ns

RDS = H

7

ns

RDS = L

Fall Time

7

ns

RDS = H

6

ns

RDS = L

SERIAL BUS TIMING

Data Valid before DC Clock

26%

74%

UI

Data Valid after DC Clock

26%

74%

UI

Serial Set Time

400

ps

Serial Hold Time

400

ps

Transition Time

Master

20% to 80%

200

ps

(1)

(2)

Rise and Fall Time tested on the following pins only: WR* and RD*.

(3)

Specification is ensured by characterization and is not tested in production.

(4)

Specification is ensured by design and is not tested in production.

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