Read Command

Read Data

TA"

a

r

c

c

c

c

c

c

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD8

RD9

RD10

RD11

RD12

RD13

RD14

RD15

RD16

RD17

RCRC0

RCRC1

RCRC2

RCRC3

RCRC4

h

h

l

l

l

l

h

Read Data

Read Data

A

A

B

B

C

C

TA'

TA'

IDLE, Write or

READ

DC

DD

LM4308

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SNLS225C – AUGUST 2007 – REVISED MAY 2013

READ TRANSACTION

The READ transaction is similar to the WRITE but longer. The full serial READ transaction is shown in

Figure 10 . CRC bits protect both the READ command sent from the Master to the Slave (C[0:4] bits), and also

the Data sent back from the Slave to the Master (RC[0:4] bits). The READ transaction consists of four sections.

In the first section the Master sends a READ Command to the Slave. This command is the same as a WRITE,

but the R/W serial bit is set High and the data payload is ignored. The CRC bits are used to ensure that the

transaction is valid and prevents a false READ from being entered. The Control Input "Write Only - WO" on the

Slave must be set to WRITE & READ mode (Low) to support READ transactions.

In the second section (TA') the DD line is turned around, such that the Master becomes the DD Receiver and

Slave becomes the DD Line Driver. The Slave will drive the DD line High after a fixed number of DC cycles. This

ensures that the DD lines are a stable High state and that the High-to-Low transition of the "Start" bit is seen by

the Master.

The third section consists of the transfer of the read data from the Slave to the Master. Therefore the back

channel data signaling rate is ¼ of the forward channel (Master-to-Slave direction). When the Slave transmits

data back to the Master, it drives the DD line Low to indicate start of read data, followed by the actual read data

and CRC payload.

The fourth and final section (TA") occurs after the read data has been transferred from the Slave to the Master.

In the fourth section the DD line is again turned around, such that the Master becomes the transmitter and the

Slave becomes the receiver. The Slave drives the DD line High for 1 bit and then turns off. The DD lines are OFF

momentarily to avoid driver contention. The Master then drives the DD line High for 1 bit time and then idles the

bus until the next transaction is sent (WRITE or another READ).

Figure 10. READ Transaction

The READ transaction requires a dual cycle on the Master input to complete. Once the first READ is done

(RDCycle1) the serial link is busy until the second READ (RDCycle2) is done. The Host may do transactions to

other devices between the READs, just not to CS1* or CS2*. On the first READ, the CS1* or CS2* line is driven

low and the RD* pulses low. A fixed Data Word of all Lows is returned and should be ignored by the Host. The

requested data will be available at the Master after 480 DC cycles. The second READ should now be done to

collect the requested data. Upon the READ from the host, the Master will turn ON its 18 data drivers and output

the data to the Host and then turn them off.

When the READ is received, the Data output buffers turn off to avoid contention. After 140 DC cycles the RD*

signal switches Low. It then switches High after another 62 DC cycles and latches in the Data from the Display.

The CRC is then calculated and sent to the Master. To avoid floating the inputs to the Display, the Slave data

outputs are turned back on.

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