CLK

CS2*

D0

WR*

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

ERR

AD

DD

DC

A

1

7

TOP VIEW

MASTER

CS1*

PD*

D17

RD*

Notes:

Static and Supply signals not shown.

Inner row may also use via in escape.

D17

D16

D14

D15

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WR*

CS2*

AD

CS1*

A

1

7

SLAVE

PD*

ERR

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Figure 18. SLVS Interface Layout

FLEX CIRCUIT RECOMMENDATIONS

A differential 100 Ohm transmission path will yield the best results and be matched to the integrated differential

termination resistance. Also, the interconnect should employ a coupled lines to ensure that the majority of any

noise pick up is common-(equal on both the P and N signals) so that it is rejected by the differential receiver. A

GSSGSSG pinout is recommended. Depending on external noise sources, shielding maybe required.

GROUNDING

Even though the serial Data and Clock signals are differential, a common ground signal is still required. This

provides a common ground reference between the devices and a current return path for the common mode

current.

GENERAL GUIDELINES and RECOMMENDATIONS FOR PCB DESIGN

LVCOMS Signals:

•

To reduce EMI, avoid parallel runs with fast edge, large LVCMOS swings.

•

To reduce crosstalk allow enough space between traces. It is recommended to distance the centers of two

adjacent traces at least four times the trace width. To improve design performance, lower the distance

between the trace and the ground plane to under ~ 10 mils.

•

Keep clock trace as straight as possible. Use arc-shaped traces as an alternative to the right-angle bends.

•

Do not use multiple signal layers for clock signals.

•

Do not use vias in clock transmission lines, as vias can cause impedance change and reflection.

SLVS Signals:

•

Floor plan, locate Master near the connector to limit chance of cross talk to high speed serial signals.

•

Use differential routing techniques. (i.e., match the lengths as well as the turns that each trace goes through)

•

Keep the length of the two differential traces the same to minimize the skew and phase difference.

•

Route serial traces together, minimize the number of layer changes to reduce loading.

22

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