LM4308 datasheet(14/33 Pages) TI

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DATA[17:0]

WR*

RD*

SLAVE

OUTPUT

CS1* or CS2*

other CS* = H

Display Driver ON

T10

SLV ON

DATA[17:0]

RD*

CS1* or CS2*

other CS*=H

MASTER

INPUT

WR*

DATA

LOW

RDcycle1

RDcycle2

DATA

VALID

T5a

SLV Outputs Update

Data, AD, CS1*, CS2*

as needed

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Figure 11. Master Input READ Timing

Figure 12. Slave Output READ Timing

Table 6. i80 CPU READ Interface Parameters

No.

Parameter

Min

Typ

Max

Units

MasterOUT

Data and address valid after RD* High-to-Low

MasterOUT

Data and address valid after RD* Low-to-High

MasterIN

Delay Time Between READs

500

MasterIN

Delay Time Until Data Available (RDcyc2)

480

Master

Master Latency

DC Cycles

T5a

Slave

Slave Latency, (not shown)

158

DC Cycles

Slave

AD Set Time before RD* High-to-Low

140

DC Cycles

Slave

RD* Pulse Low Width

DC Cycles

Slave

Data Set Time

DC Cycles

Slave

Data Hold Time

T10

Slave

Slave Data Outputs

DC Cycles

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