Single-Ended

Differential

(P-N)

100

300

0V

mV

P

N

Single-Ended

Differential

100

200

300

0V

+200 mV

-200 mV

mV

P

N

P-N

LM4308

www.ti.com

SNLS225C – AUGUST 2007 – REVISED MAY 2013

Figure 15. Single-ended and differential SLVS waveforms

Noise that gets coupled onto both signals, is common-mode and is rejected by the receiver. Route the traces that

form the pair together (coupled) to help ensure that noise picked up is common. Differential noise that causes a

dip in the signal but does not enter the threshold region is also rejected. Differntial noise margin is the minimum

Figure 16. SLVS common-mode rejection waveform

LM4308 Features and Operation

POWER SUPPLIES

powers the logic interface and may be powered between 1.6 and 3.0V to be compatible with a wide range of host

and target devices.

BYPASS RECOMMENDATIONS

Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ceramic

(surface mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tantalum capacitor is recommended near the

reduce resistance and inductance of the feeds. Utilizing a thin spacing between power and ground planes will

provide good high frequency bypass above the frequency range where most typical surface mount capacitors are

less effective. To gain the maximum benefit from this, low inductance feed points are important. Also, adjacent

signal layers can be filled to create additional capacitance. Minimize loops in the ground returns also for

improved signal fidelity and lowest emissions.

MASTER / SLAVE CONFIGURATION

The LM4308 device can be configured to be a Master or a Slave with the M/S* pin. For normal modes, TM (Test

Mode) input must also be Low, setting TM High enters a factory test mode.

Copyright © 2007–2013, Texas Instruments Incorporated

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