L

AD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

C0

C1

C2

C3

C4

H

DC

DD

idle

R/W* CS12

LM4308

www.ti.com

SNLS225C – AUGUST 2007 – REVISED MAY 2013

Figure 8. WRITE Transaction

WRITE TRANSACTION

The WRITE transaction consists of 14 DC cycles to send the control, data and CRC information on the DD

signal. This includes the Start Bit, AD, R/W*, CS12, D[0:17], CRC bits C[0:4] and a reserved bit (High). See

Figure 8. The data payload is sent least significant bit (LSB) first. The CS1/2 bit denotes which Chipset pin was

active. CS1/2 = HIGH designates that CS1* is active (Low). CS1/2 = LOW designates that CS2* is active (Low).

CS1* and CS2* Low is not allowed. The AD carries the information on the AD input signal. The R/W* will be Low

for a Write transaction.

Figure 9 illustrates a WRITE transaction showing Master Input, SLVS, and Slave output timing. Table 5 lists the

WRITE timing parameters.

On the Master input, an i80 style WRITE is shown. The ChipSelect (CS1* or CS2*) is Low. The WR* goes Low,

and Data and AD signals are sampled on the rising edge of the WR* signal. A tight set and hold window is

required as shown by T1 and T2. A Latency delay later (T4) the SLVS start bit will be transmitted on the DD

signal. Since it takes 14 DC cycles to send the serial word, a maximum load rate on the Master input should be

slower than this (16 DC cycles or longer). This is T3 in Figure 9.

The Slave output timing is shown in the bottom of Figure 9. Note that the SLV output timing is different than the

MST input timing, however the same information is conveyed. T5 is the latency delay of the Slave and also the

serial payload length. Once the start bit is received, it will take this long for the SLV output to update. First, the

Data[0:17], AD and CS* bits will update as required. One DC cycle later the WRITE signal will transition Low for

12 DC cycles. Then the WRITE signal will transition High and the Display will latch the data. There is a minimum

hold time of one DC cycle (T9). This hold time can (will) be longer as the outputs hold their last state until the

next transition is received. Also note that the CS1* and CS2* signals also hold their last state until they need to

change. This would occur if a transaction is received for the other CS* signal, or if the Slave enters Power Down

(PD*=L).

Copyright © 2007–2013, Texas Instruments Incorporated

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