LM4308 datasheet(20/33 Pages) TI

20 / 33 page

LM4308 (Slave)

Notes:

1. PCON1, PCON0 = Low = x 8 Mode

2. Bypass Capacitor Values :

C1, C2 = 4.7 PF

C3 = 2.2 PF

C4 = 0.1 PF

LM4308 (Master)

CLK

PD*

RD*

CS2

PCON1

PCON0

DDP_M

DDN_M

VSSI/O

1.8V

DCP_M

DCN_M

VSSI/O

VSS

VSSA

WR*

CS1

MS*

ERR

D10

D11

D12

D13

D14

D15

D16

D17

PD*

RDS0

RDS1

DDP_S

DDN_S

VSSI/O

1.8V

DCP_S

DCN_S

VSSI/O

VSS

VSSA

MS*

ERR

A/D

(Other Devices)

BaseBand

Processor

CLK

Tree

D10

D11

D12

D13

D14

D15

D16

D17

CS2

WR*

CS1

A/D

RD*

Main

Display

(Buffered)

Sub Display

(Buffered)

Optional

VDDIO

VDDA

VDD

1.8V

VDDIO

VDDA

VDD

Notes:

1. RDS0 and RDS1 are VDDIO dependent. If/When VDDIO = 3.0V, RDS0

and RDS1 should be strapped low.

2.Bypass Capacitor Values :

C1,C2 = 4.7 PF

C3 = 0.1 PF

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Figure 17. Dual SMART Display Application

The Slave recovers the serial signals and generates the parallel bus for the Display(s). The Slave VDDIO is set to

be compatible with the Displays employed. The Data bus signals are bidirectional to support both WRITEs and

READs. The other signals. AD, WR*, RD*, and CS* signals are outputs only. The connection between the Slave

device and the displays should be done such that long stubs are avoided. Extra care should be taken on the

WR* and RD* signal layouts as these signals rely on the signal edges to latch the data. The Slave has user

adjustable edge rate controls for the parallel bus outputs. This can be used to optimize the edge rate vs the

required VDDIO magnitude. Also, independent control of the strobe (WR* and RD*) is supported. This allows for

the strobe signal to retain sharp edges, while using softer edges on the wide parallel data bus signals. This aids

in noise reduction. The Slave also provides a ERR pin to flag any CRC errors detected. This signal maybe routed

back to the host for monitoring, or bought out to a test point. The Slave supports a WRITE ONLY mode (READ

operation and serial bus turn around is prevented). This mode is obtained by setting the WO pin to a logic High.

The Sleep state of the display may be entered by driving the PD* signal to a logic Low. Outputs are then set to

their Power Down de-asserted states. Several configuration pins are also required to be set. For a Slave, tie

M/S* = L, TM = L, and WO and RDS[1:0] to the desired setting. If only one display is required in the application,

the unused CS output signal should be left un-connected.

In this application, WRITEs and READs for the Displays are serialized and sent to the displays. Transaction to

other devices on the shared bus (MST input) are ignored by the Master.

SYSTEM TIMING CONSIDERATIONS

When employing the SERDES chipset in place of a parallel bus, a few system considerations must be taken into

account. Before sending commands (i.e. initialization commands) to the display, the SERDES must be ready to

transmit data across the link. The serial link must be powered up, and the PLL must be locked. Also, a review of

the Slave output timing should be completed to insure that the timing parameters provided by the Slave output

meet the requirements of the LCD driver input. Specifically, pulse width on WR* and RD*, data valid time, and

bus cycle rate should be reviewed and checked for display compatibility. Additional details are provided next:

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