MASTER INPUT

DATA[17:0]

AD

RD*

WR*

CS1*

CS2*

SERIAL

DC

DD

SLAVE OUTPUT

DATA[17:0]

AD

CS1*

CS2*

Word N

Word N+1

Word N to CS1*

Word N+1 to CS1*

L

L

WR*

RD*

idle

idle

LM4308

www.ti.com

SNLS225C – AUGUST 2007 – REVISED MAY 2013

SLAVE OUTPUT TIMING / DISPLAY COMPATIBILITY

Compatibility of target device’s timing requirements should be checked. Check that the Slave WR* active low

pulse is wide enough for the target display(s). If the Slave output is too fast, a slower DC rate should be chosen

(PLL setting or CLK rate may be adjusted). See SYSTEM CONSIDERATION section also.

Figure 13 illustrates the timing of two writes being sent to CS1*. Note that on the Slave output for Word N, that

the DATA, AD, and CS signals hold their last state until the next transaction is received. This effectively extends

the Hold time after Word N’s WRITE rise. The length of this period (idle) is determined by the time until the next

transaction on the Master input. When the second write is received (Word N+1) the Data, AD, and CS signals

update as needed. Note that the active CS signal stay low until a transaction to the other CS is received or the

Slave is put into powerdown.

Figure 13. Timing Example - Two WRITEs to CS1*

CYCLIC REDUNDANCY CHECK (CRC)

The CRC is used to detect errors in both WRITE and READ transactions on the serial link. The LM4308 uses a

5-bit CRC field to detect errors in the 22-bit payload. The Transmitting device calculates the CRC and appends it

to the payload. The Receiver also calculates the CRC and compares it to the received CRC. If they are the

same, the transmission is error free. If they are different, the ERR pin then flags the error.

CRC provides a better coverage than a parity bit, which can only flag one half of the possible errors. The CRC is

calculated by taking the payload and adding 5 zeros and then dividing by a fixed number. The remainder of the

calculation is the 5-bit CRC field that is transmitted.

If a CRC error handling is shown in the table below. See also Figure 14.

Table 7. CRC Error Response

Operation

Direction

Error

Response

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