A

B

C

D

E

F

G

1

2

3

4

5

6

7

Ball A1

LM4308

www.ti.com

SNLS225C – AUGUST 2007 – REVISED MAY 2013

•

Use ground lines are guards to minimize any noise coupling (specifies distance).

•

Avoid using multiple vias to reduce impedance mismatch and inductance.

•

Use a GSSGSSG pinout in connectors (Board to Board or ZIF).

•

Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low

inductance feeds.

•

High current returns should have a separate path with a width proportional to the amount of current carried to

minimize any resulting IR effects.

•

Slave device - follow similar guidelines.

•

see AN-1126 (SNOA021) (BGA) and AN-1187 (SNOA401) (WQFN) also

Connection Diagram csBGA Package

Figure 19. TOP VIEW

(not to scale)

Note that the pinout of a MASTER configured device is DIFFERENT than a SLAVE configured device. The use

of two logic symbols for PCB schematic is recommended.

Table 8. CPU Master Pinout

MST

1

2

3

4

5

6

7

A

AD

CS1*

PD*

DCP_M

DCN_M

DDN_M

DDP_M

B

CLK

TM

M/S*

PLLCON0

PLLCON1

C

WR*

CS2*

ERR

D17

D

RD*

D16

E

D0

D1

D14

D15

F

D2

D3

D6

D9

D11

D13

G

D4

D5

D7

D8

D10

D12

Table 9. CPU Slave Pinout

SLV

1

2

3

4

5

6

7

A

AD

CS1*

PD*

DDP_S

DDN_S

DCN_S

DCP_S

B

WO

TM

M/S*

RDS0

RDS1

C

WR*

CS2*

ERR

D17

D

RD*

D16

E

D0

D1

D14

D15

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