LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

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UNUSED/OPEN LVCMOS PINS

Unused inputs must be tied to the proper input level — do not float them. Unused outputs should be left open to

minimize power dissipation.

LVCMOS MASTER INPUT PINS

not High-Z with power supplies OFF. If communication between the Host (i.e. BBP) and other devices (i.e.

Memory) is required when the display is not ON; the power to the Master must be ON, and the Master should be

in SLEEP mode (by CLK Stop or PD*=L). In this condition, Master inputs are High Z and will not load (or clamp)

MASTER CLOCK INPUT

The Master Clock input is a special 3.3V Tolerant input pin. This allows the clock tree to be powered from a

PLLCON1

PLLCON0

Multiplier

CLK Range

0

0

8

9.6 to 30 MHz

0

1

10

9.6 to 24 MHz

1

0

12

9.6 to 20 MHz

1

1

Reserved

Reserved

PHASE-LOCKED LOOP

When the LM4308 is configured as a Master, a PLL is enabled to generate the serial link clock. The Phase-

locked loop system generates the serial data clock at several multiples of the input clock. The DC rate is limited

to 240 MHz. The PLL multiplier is set via the PLLCON[1:0] pins. Multipliers of 8X, 10X and 12X are available.

For example, if the input clock is 19.2MHz, and a 8X multiplier is selected, DC will be 153.6 MHz. and the DD

line rate is 307.2 Mbps (raw bandwidth).

POWER DOWN OUTPUT STATES

When the device is in the SLEEP state (PD*=L) the output pins will be driven to the states shown in the table

below.

Device

Signal

State in Power Down

Slave

Data[17:0]

Low

Slave

CS1*, CS2*, WR*, RD*, AD

High

Slave

ERR

Low

Master

ERR

Low

SLAVE

Upon application of power to the SLV device, all outputs are turned on and held in their de-asserted states.

MASTER

Upon application of power to the MST device, the ERR output is ON, and is logic low (normal mode).

SLEEP MODE OPTIONS

The Master can enter sleep mode by three options. The PD* pin is driven low, the clock input is stopped, or if the

power supplies are turned off.

The simplest option is a control signal to drive the PD* input. When PD* input is driven low, the device enters a

sleep mode and supply current is minimized. This mode also supports high-Z Master LVCMOS inputs. The

second option is with Power ON, PD* = H, and the CLK input is stopped. The CLK stop state is recommend to

be logic Low. The Master detects this state and enters the sleep state. The third option is to cut power to the

device. In this configuration the LVCMOS inputs are not High-Z due to internal diodes for ESD protection.

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