LM4308

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SNLS225C – AUGUST 2007 – REVISED MAY 2013

The serial link should be started up as follows: The chipset should be powered. During power up, the PD* inputs

should be held Low and released once power is stable and within specification and link transmission is desired.

Before data can be sent across the serial link, the link must be ready for transmission. The CLK needs to be

applied to the MST, and the PLL locked. This is controlled by a keep-off counter set for 1024 CLK cycles. After

the PLL has locked and the counter expired, transmission may now occur. For a 19.2MHz application is is less

than 54µs delay. If a WRITE is done to the display during this time, it will be lost and the display may not be

properly configured. Ensure that the FIRST WRITE to the display is done AFTER the link is ready for

transmission.

It takes 14 DC Cycles to send a 18-bit CPU Write including the serial overhead. The DC cycle time is calculated

based on the PLL Multiplier setting and also the input clock frequency. For example, a 19.2 MHz input CLK and

a 8X PLLCON[1:0] setting yields a DC frequency of 153.6 MHz. Thus it takes

∼100 ns to send the word in serial

form. To allow some idle time between transmissions (this will force a bit sync per word if the gap is long enough

in between), the load rate on the Master input should not be faster than 16 DC cycles, or every 105 ns (9.6 MT/s)

in our example to support a data pipe line. This is sometimes referred to as the bus cycle time (time between

commands). Thus the time between WRITEs on the Master Input MUST NOT be faster than 105 ns, otherwise

the FIFO will overflow and data will be lost.

The Slave output WR* and RD* timing is a function of DC cycles alone. The width of the WR* pulse low is

TWELVE DC cycles regardless of the pulse width applied to the Master input. In the 19.2MHz & 8X application,

the WR* pulse low will be 78 ns. System designers need to check compatibility with the display driver to ensure

that this pulse width meets its requirement. If it is too fast, select a lower PLL Multiplier or apply a slower input

clock.

PCB LAYOUT – SERIAL SIGNALS

The LM4308 provides a swap function of SLVS DD and DC lines depending upon the state of the M/S* pin. This

facilitates a straight through via-less SLVS interface design eliminating the needs for via and crossovers as

shown on Figure 18. It is recommended to use separate logic symbols for the Master and the Slave to avoid

layout errors.

NOTE

THE PINOUT IS DIFFERENT FOR A MASTER AND SLAVE CONFIGURED DEVICE.

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