Main

Display

(Buffered)

Sub

Display

(Buffered)

Optional

DD

LM4308

Slave

Apps

Processor

---

Graphics

Processor

---

Baseband

Processor

PD*

LM4308

Master

DC

PLL

M/S*

PLLCON[1:0]

TM

D[17:0]

CS2*

AD

PWR

Config.

CLK

CLK

Tree

(other devices)

(Bypass Caps

not shown)

1.8V

GND

GND

PD*

CS1*

PWR

Config.

TM

M/S*

RDS[1:0]

ERR

1.8V

2.8V

GND

D[17:0]

WR*

CS2*

CS1*

AD

RD*

RD*

WR*

ERR

WO

LM4308

www.ti.com

SNLS225C – AUGUST 2007 – REVISED MAY 2013

LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave

Check for Samples: LM4308

1

FEATURES

DESCRIPTION

The LM4308 device adapts a 18-bit CPU style display

2

•

18-bit i80 CPU Display Interface

interfaces to a MPL-2 SLVS differential serial link for

•

Supports up to 640 x 480 VGA Formats

displays. Two chip selects support a main and sub

•

Differential SLVS Interface

display up to and beyond 640 x 480 pixels. A mode

pin configures the device as a Master (MST) or Slave

•

Dual Displays Supported

(SLV). Both WRITE and READ operations are

•

WRITE and READ Operations Supported

supported. CPU interface widths below 18-bits are

•

Robust Differential Physical Layer

supported by tieing unused inputs to a static level.

•

400mVpp Differential Signal Swing

The differential line drivers and receivers conform to

•

Internal 100

Ω Termination Resistor

the JEDEC SLVS Standard. When noise is picked up

as common-mode, it is rejected by the receivers. This

•

Low Power Consumption

is

further

enhanced

with

the

50

Ohm

output

•

5-bit CRC for Data Integrity

impedance of the drivers. The 100 Ohm termination

•

Level Translation between Host and Display

is integrated into the receivers.

•

Low Power Sleep State

Data integrity is insured with a 5-bit CRC field. CRC

•

3.3V Tolerant Master Clock Input Regardless

checking is done for both WRITE and READ

operations.

An

Error

(ERR)

pin

reports

the

occurrence of an error. A Write Only mode is also

•

Fast Start Up Time - 1k CLK Cycles

provided.

•

1.6V to 2.0V Core / Analog Supply Voltage

The interconnect is reduced from 23 signals to only 4

•

1.6V to 3.0V I/O Supply Voltage Range

active signals with the LM4308 chipset easing flex

interconnect design, size constraints and cost.

SYSTEM BENEFITS

A low power sleep state entered when the PD* inputs

•

Small Interface

are driven low.

•

Low Power

•

Low EMI

•

Intrinsic Level Translation

Typical Application Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.