LM4308 datasheet(2/33 Pages) TI

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LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Pin Descriptions

Description

No.

Pin Name

of Pads

of Pins

I/O, Type(1)

CPU Master

CPU Slave

uArray

WQFN

(MST)

(SLV)

SLVS SERIAL BUS PINS

DDP

IO, slvs

Differential Data - Positive, Transceiver

DDN

IO, slvs

Differential Data - Negative, Transceiver

DCP

O, I, slvs

Differential Clock - Positive,

Line Driver

Receiver

DCN

O, I, slvs

Differential Clock - Negative,

Differential Clock - Clock,

Line Driver

Receiver

CONFIGURATION/PARALLEL BUS PINS

M/S*

High for Master

Low for Slave

LVCMOS

Test Mode Control Input

LVCMOS

Tie Low

L = Normal

H = Test Mode (factory test only)

PLLCON[1:0]

PLL Multiplier Input Pins

LVCMOS

See Table 1

RDS[1:0]

Receiver Drive Strength Control Input

LVCMOS

Pins,

See Table 2

ERR

Error Output Signal

LVCMOS

Indicates a CRC error on the READ

Reports a CRC error was detected on

Payload

the WRITE Payload

WRITE Only Control Input

LVCMOS

L = Writes and reads enabled

H = Write Only

CLOCK / POWER DOWN SIGNALS

CLK

CLK Input

LVCMOS

Input is 3.3V Tolerant regardless of

VDDIO

PD*

Power Down Input,

LVCMOS

L = Powered down, Low Power SLEEP state

H = active state

PARALLEL INTERFACE SIGNALS

D[17:0]

IO,

CPU Data Bus Inputs / Outputs

CPU Data Bus Outputs / Inputs

LVCMOS

CS1*

I, O,

Chip Select Input Pins

Chip Select Output Pins

CS2*

LVCMOS

Only one CS is allowed to be Low at a

time.

RD*

I, O,

Read Enable Input,

Read Enable Output,

LVCMOS

active Low

WR*

I, O,

Write Enable Input,

Write Enable Output,

LVCMOS

active Low

I, O,

Address / Data selector input

Address / Data selector output

LVCMOS

POWER/GROUND PINS

VDDA

Power

Power Supply Pin for the PLL (MST) and SLVS Interface. 1.6V to 2.0V

VSSA

Ground

Ground Pin for the PLL (MST) and SLVS Interface.

VDD

Power

Power Supply Pin for the digital core. 1.6V to 2.0V

VSS

Ground

Ground Pin for the digital core.

VDDIO

Power

Power Supply Pin for the parallel interface I/Os. 1.6V to 3.0V

VSSIO

Ground

Ground Pin for the parallel interface I/Os.

For the WQFN Package, VSSIO and VSS

(1)

Note: I = Input, O = Output, IO = Input/Output. Do not float input pins.

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