DATA, AD, CS

(SLV)

WR*(SLV)

ERR(SLV)

RD*(Host)

DATA (MST)

ERR(MST)

ERR

Slave

WRITE

ERR

Master

READ

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Table 7. CRC Error Response (continued)

Write

Master-to-Slave

CRC error

Slave Flags, ERR pins remains High until

PD* cycle or Power cycle, Data is written to

the display

Read

Master-to-Slave

CRC error

Slave Flags, ERR pins remains High until

Command

PD* cycle or Power cycle, Slave does

nothing

Write

Master-to-Slave,

CRC error, Serial R/W* bit

Slave Flags, ERR pins remains High until

Slave WO = H

error

PD* cycle or Power cycle, Data is written to

(False Read)

the display (write expected)

Read Data

Slave-to-Master

CRC error

Master Flags, ERR goes High, then Low

after 2nd READ, Data = X

Read Data

Slave-to-Master

Read Data not received by

Master times out, drives all Low data, then

Master

on 2nd READ cycle ERR goes High

1 = CS1* active which is a High, and 2 = CS2* active which is a Low

Figure 14. CRC - ERR Output Timing

SLVS INTERFACE

Scalable Low Voltage Signaling is the differential interface used for the physical layer of the serial (Data and

Clock) signals. The differential signal is a 200mV (typ) swing with a 200mV offset from ground. This generates a

±200mV (400mVpp) across the integrated termination resistor for the receiver to recover. The receiver detects

the differential signal and converts it to a LVCMOS signal. Noise picked up along the inteconnect is seen as

common-mode by the receiver and rejected. The low output impedance of the line driver and of the termination

network help to minimize couple noise also.

16

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