40

39

38

37

36

35

34

33

32

31

TM

CS1*

M/S*

PD*

DCN

DDN

DDP

D8

D9

D11

D10

NC

D4

D5

D6

D7

LM4308SQ

TOP VIEW

40 Lead WQFN

5mm x 5mm x 0.8mm

0.4mm pitch

(not to scale)

M/S*=H, MASTER

(DAP connection, center pad = GND)

DCP

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

TM

CS1*

M/S*

PD*

DDN

DCN

DCP

D8

D9

D11

D10

NC

D4

D5

D6

D7

LM4308SQ

TOP VIEW

40 Lead WQFN

5mm x 5mm x 0.8mm

0.4mm pitch

(not to scale)

M/S*=L, SLAVE

(DAP connection, center pad = GND)

DDP

11

12

13

14

15

16

17

18

19

20

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Table 9. CPU Slave Pinout (continued)

SLV

1

2

3

4

5

6

7

F

D2

D3

D6

D9

D11

D13

G

D4

D5

D7

D8

D10

D12

Connection Diagram - WQFN Package

Figure 20. TOP VIEW — (not to scale)

Note that the pinout of a MASTER configured device is DIFFERENT than a SLAVE configured device. The use

of two logic symbols for PCB schematic is recommended.

Table 10. CPU Master - Slave Pad Assignments

Pin #

Master

Slave

Pad #

Master

Slave

1

AD

21

D12

2

CLK

WO

22

D13

3

CS2*

23

D14

4

WR*

24

D15

5

RD*

25

D16

6

26

7

D0

27

D17

8

D1

28

ERR

9

D2

29

PLLCON1

RDS1

10

D3

30

PLLCON0

RDS0

11

D4

31

DDP_M

DCP_S

12

D5

32

DDN_M

DCN_S

13

D6

33

14

D7

34

DCN_M

DDN_S

15

NC

35

24

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