FLEX10KA datasheet(119/128 Pages) ALTERA

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Altera Corporation

119

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1)

All timing parameters are described in Tables 32 through 37 in this data sheet.

(2)

Using an LE to register the signal may provide a lower setup time.

(3)

This parameter is specified by characterization.

ClockLock &

ClockBoost

Timing

Parameters

For the ClockLock and ClockBoost circuitry to function properly, the

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

configuration, the ClockLock and ClockBoost circuitry will lock onto the

clock during configuration. The circuit will be ready for use immediately

after configuration. Figure 31 illustrates the incoming and generated clock

specifications.

Figure 31. Specifications for the Incoming & Generated Clocks

The tI parameter refers to the nominal input clock period; the tO parameter refers to the

nominal output clock period.

Table 113 summarizes the ClockLock and ClockBoost parameters.

tCLK1

tINDUTY

tI ± fCLKDEV

tI ± tINCLKSTB

tOUTDUTY

tO + tJITTER

tO – tJITTER

Input

Clock

ClockLock-

Generated

Clock

Table 113. ClockLock & ClockBoost Parameters

(Part 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Input rise time

2ns

Input fall time

2ns

tINDUTY

Input duty cycle

fCLK1

Input clock frequency (ClockBoost clock multiplication factor equals 1)

MHz

tCLK1

Input clock period (ClockBoost clock multiplication factor equals 1)

12.5

33.3

fCLK2

Input clock frequency (ClockBoost clock multiplication factor equals 2)

MHz

tCLK2

Input clock period (ClockBoost clock multiplication factor equals 2)

62.5

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