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UM0434 Datasheet(PDF) 104 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 104 Page - STMicroelectronics

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UM0434
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4.19.2
Parallel signature status register (PSSR)
PSSR, shown in
Table 93, provides status relative to operation of the parallel signature unit.
The PSSR register fields are described in
Table 94.
.
4.19.3
Parallel signature high register (PSHR)
The PSHR, shown in
Table 4.19.4, provides signature information for the high word (bits 63–
32) of the AHB data read and data write buses. Writing PSHR initializes a seed value before
enabling signature accumulation. PSCR[INIT] may also be used to clear the PSHR. PSHR
is unaffected by system reset, thus should be initialized by software before performing
parallel signature operations.
62
WREN
Write enable.
0 Processor write cycles are ignored.
1 Processor write cycles are accumulated. For inactive byte lanes, zeros
are used for the data values.
63
INIT
This bit can be written with a 1 to set the values in the PSHR, PSLR, and PSCTR
registers to all 0s. (0x00000000). This bit always reads as 0.
Table 92.
PSCR field descriptions (continued)
Bits
Name
Description
Table 93.
parallel signature status register (PSSR)
32
62
63
Field
—
TERR
Reset
Unaffected
R/W
—
w1c
DCR
DCR 273
Table 94.
PSSR field descriptions
Bits
Name
Description
32–62
—
Reserved, should be cleared.
63
TERR
Transfer error status. Indicates whether a transfer error occurs on accumulated read
data and that the read data values returned are ignored and 0s are used instead.
Hardware does not clear TERR; only a software write of 1 to TERR clears it.
0 No transfer error on accumulated read data since software last cleared
this bit.
1 A transfer error occurred on accumulated read data since software last
cleared this bit.



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