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Instruction model

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Instruction model

This chapter provides additional information about the Book E architecture as it relates

specifically to the e200z3.

The e200z3 is a 32-bit implementation of the Book E architecture. The Book E architecture

specification includes a recognition that different processor implementations may require

clarifications, extensions, or deviations from the architectural descriptions. Book E

instructions are described in the

EREF: A Programmer's Reference Manual for Freescale

Book E Processors.

5.1

Operand conventions

This section describes operand conventions as they are represented in the Book E

architecture. These conventions follow the basic descriptions in the classic PowerPC

architecture with some changes in terminology. For example, distinctions between user- and

supervisor-level instructions are maintained, but the designations—UISA, VEA, and OEA—

do not apply. Detailed descriptions are provided on conventions used for storing values in

registers and memory, for accessing processor registers, and for representing data.

5.1.1

Data organization in memory and data transfers

Bytes in memory are numbered consecutively starting with 0. Each number is the address

of the corresponding byte.

Memory operands can be bytes, half-words, words, or double-words (consisting of two 32-

bit elements) or, for the load/store multiple instruction type, a sequence of bytes or words.

The address of a memory operand is the address of its first byte (that is, of its lowest-

numbered byte). Operand length is implicit for each instruction.

5.1.2

Alignment and misaligned accesses

The e200z3 core provides hardware support for misaligned memory accesses; however,

there is performance degradation for accesses that cross a 64-bit (8-byte) boundary. For

loads that hit in the cache, the throughput of the load/store unit is degraded to 1 misaligned

load every 2 cycles. Stores misaligned across a 64-bit (8 byte) boundary can be translated

at a rate of 2 cycles per store. Frequent use of misaligned memory accesses is discouraged

because of the impact on performance.

Note:

Accesses that cross a translation boundary may be restarted. A misaligned access that

crosses a page boundary is restarted entirely if the second portion of the access causes a

TLB miss. This may result in the first portion being accessed twice.

Accesses that cross a translation boundary where the endianness changes cause a byte-

ordering data storage interrupt.

Note:

lmw, stmw, lwarx, and stwcx. instructions that are not word aligned cause an alignment

exception.

5.1.3

e200z3 Floating-Point implementation

The e200z3 core does not implement the floating-point instructions as they are defined in

Book E. Attempts to execute a Book E–defined floating-point instruction result in an illegal

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