UM0434 datasheet(111/390 Pages) STMICROELECTRONICS

111 / 390 page

Instruction model

UM0434

112/391

be decoded and resolved. The instruction fetch unit predicts the direction of the branch as

follows:

●

Predict not taken for any branch whose fetch address misses in the BTB or hits in the

BTB and is predicted not taken by the counter.

●

Predict taken for any branch that hits in the BTB and is predicted taken by the counter.

Note that the static branch prediction bit defined by the Book E architecture in the BO

operand is ignored.

5.9

Interruption of instructions by interrupt requests

In general, the e200z3 core samples pending external input and critical input interrupt

requests at instruction boundaries. However, in order to reduce interrupt latency, long-

running instructions may be interrupted prior to completion. Instructions in this class include

divides (divw[uo][.], efsdiv, evfsdiv, evdivw[su]), Load Multiple Word (lmw), and Store

Multiple Word (stmw). When an instruction is interrupted before completion, the value saved

in SRR0/CSRR0 is the address of the interrupted instruction.

5.10

e200z3-Specific instructions

The e200z3 core implements the following instructions that are not defined by the Book E

architecture:

●

The EIS-defined integer select (isel) APU consists of the isel instruction, described in

Chapter 5.10.1: Integer select APU.”

●

The Return from Debug Interrupt instruction (rfdi) is defined by the Book E debug APU.

This instruction is described in

Chapter 5.10.2: Debug APU.”

●

The signal processing extension (SPE) APU provides a set of 64-bit SIMD instructions.

These are listed in

Chapter 5.10.3: SPE APU instructions,” and described in the EREF.

●

The embedded vector and scalar single-precision floating-point APUs are listed along

with supporting instructions in

Chapter 5.10.4: Embedded vector and scalar single

precision floating point APU instructions.” These instructions are described in detail in

the

EREF.

5.10.1

Integer select APU

The integer select APU defines the Integer Select (isel) instruction, which provides a means

to select one of two registers and place the result in a destination register under the control

of a predicate value supplied by a bit in the condition register. isel can be used to eliminate

branches in software and in many cases improve performance; it can also increase program

execution time determinism by eliminating the need to predict the target and direction of the

branches replaced by the integer select function.

The isel instruction form and definition are described in the

EREF

5.10.2

Debug APU

The e200z3 implements the Book E debug APU to support the ability to handle the debug

interrupt as an additional interrupt level. To support this interrupt level, the Return from

Debug Interrupt instruction (rfdi) is defined as part of the debug APU, along with a pair of

save/restore registers, DSRR0, and DSRR1.

UM0434 Datasheet(PDF) 111 Page - STMicroelectronics

UM0434 Datasheet(HTML) 111 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL