UM0434 datasheet(121/390 Pages) STMICROELECTRONICS

121 / 390 page

Instruction model

UM0434

122/391

Options for embedded floating-point APU implementations

Table 108 lists implementation options allowed by the embedded floating-point architecture

and describes how the e200z3 handles those options.

5.11

Unimplemented SPRs and read only SPRs

The e200z3 fully decodes the SPR field of mfspr and mtspr instructions. If the SPR

specified is undefined and not privileged, an illegal instruction exception is generated. If the

SPR specified is undefined and privileged and the CPU is in user mode (MSR[PR] = 1), a

privileged instruction exception is generated. If the SPR specified is undefined and

privileged and the CPU is in supervisor mode (MSR[PR] = 0), an illegal instruction exception

is generated.

For mtspr, if the SPR specified is read-only and not privileged, an illegal instruction

exception is generated. If the SPR specified is read-only and privileged and the CPU is in

user mode (MSR[PR] = 1, a privileged instruction exception is generated. If the SPR

specified is read-only and privileged and the CPU is in supervisor mode (MSR[PR] = 0), an

illegal instruction exception is generated.

5.12

Invalid instruction forms

Table 109 describes invalid instruction forms.

Table 108.

Embedded floating-point APU options

Option

e200z3

Implementation

Overflow and underflow conditions may be signaled by doing exponent evaluation of the

operation. If an examining of the exponents determines that an overflow or underflow

could occur, the implementation may choose to signal an overflow or underflow.

Follows the

recommendation; does

not use the estimation.

If an operand for a calculation or conversion is denormalized, the implementation may

choose to use a same-signed zero value in place of the denormalized operand.

Uses a same-signed

zero value in place of

the denormalized

operand.

+Infinity and -Infinity rounding modes are not required to be handled by an

implementation. If an implementation does not support ±Infinity rounding modes and the

rounding mode is set to be +Infinity or -Infinity, an embedded floating-point round

interrupt occurs after every floating-point instruction for which rounding may occur,

regardless of the value of FINXE, unless an embedded floating-point data interrupt also

occurs and is taken.

Supports rounding to ±

Infinity.

For absolute value, negate, and negative absolute value operations, an implementation

may choose either to simply perform the sign bit operation recognizing interrupts or to

compute the operation and handle exceptions and saturation where appropriate.

A sign bit operation is

performed; interrupts

are taken.

SPEFSCR FGH and FXH bits are undefined upon the completion of a scalar floating-

point operation. An implementation may choose to clear them or leave them unchanged.

Always clears these bits

for such operations.

An implementation may choose to only implement sticky bit setting by hardware for

FDBZS and FINXS, allowing software to manage the other sticky bits. It is recommended

that all future implementations implement all sticky bit settings in hardware.

Implements all sticky bit

settings in hardware.

UM0434 Datasheet(PDF) 121 Page - STMicroelectronics

UM0434 Datasheet(HTML) 121 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL