UM0434 datasheet(122/390 Pages) STMICROELECTRONICS

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UM0434

Instruction model

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5.13

Instruction summary

In addition to the SPE instructions listed in

Table 106 and the floating-point instructions

listed in

Table 107, the e200z3 implements the instructions defined in Table 110 and

Table 111. Instructions not listed in these tables are not supported by the e200z3 core and

signal an illegal, unimplemented, or floating-point unavailable exception. Implementation-

dependent instructions are identified with a footnote.

Note:

Specific APUs are not included in the table below:

●

SPE APU

●

VLE extension

5.13.1

Instruction index sorted by mnemonic

Table 110 lists instructions by mnemonic.

Table 109.

Invalid instruction forms

Instructions

Descriptions

Load and

store with

update

Book E defines as an invalid form the case when a load with update instruction specifies the same

instruction and updates the register with the load data. In addition, if rA = 0 for any load or store with

update instruction, the e200z3 core updates rA (GPR0).

Load Multiple

Word (lmw)

Book E defines as invalid any form of lmw instruction in which rA is in the range of registers to be

loaded, including the case in which rA = 0. On the e200z3, invalid forms of lmw execute as follows:

– Case 1: rA is in the range of rD, rA

≠ 0. In this case address generation for individual loads to

of this lmw instruction. rA is overwritten with a value fetched from memory as if it had not been the

base register. Note that if the instruction is interrupted and restarted, the base address may be

different if rA has been overwritten.

– Case 2: rA = 0 and rD= 0. In this case address generation for all loads to register targets rD=0 to

rD = 31 is done substituting the value of 0 for rA.

Branch

Conditional

to Count

Link]

Book E defines as invalid any bcctr or bcctrl instruction that specifies the decrement and test CTR

(BO[2] = 0) option. The e200z3 executes instructions with these invalid forms by decrementing the

CTR and branching to the location specified by the pre-decremented CTR value if all CR and CTR

conditions are met as specified by the other BO field settings.

Instructions

with non-

zero

reserved

fields

Book E defines certain bit fields in various instructions as reserved and specifies that these fields be

set to zero. Following the Book E recommendation, the e200z3 ignores the value of the reserved

field (bit 31) in X-form integer load and store instructions. The e200z3 ignores the value of the

reserved ‘z’ bits in the BO field of branch instructions. For all other instructions, the e200z3

generates an illegal instruction exception if a reserved field is non-zero.

Table 110.

Instructions sorted by mnemonic

Format

Opcode

Mnemonic

Instruction

Primary

(Inst0:5)

Extended

(Inst21:31)

011111

01000 01010 0

add

Add

011111

01000 01010 1

add.

Add & record CR

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