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UM0434 Datasheet(PDF) 136 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 136 Page - STMicroelectronics |
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136 / 390 page  UM0434 Instruction model 137/391 X 011111 01000 11100 0 eqv Equivalent X 011111 01000 11100 1 eqv. Equivalent and record CR X 011111 01001 10111 / lhzux Load Halfword and Zero with Update Indexed X 011111 01001 11100 0 xor XOR X 011111 01001 11100 1 xor. XOR and record CR XFX 011111 01010 00011 / mfdcr Move From Device Control Register XFX 011111 01010 10011 / mfspr Move From Special Purpose Register X 011111 01010 10111 / lhax Load Halfword Algebraic Indexed X 011111 01011 10111 / lhaux Load Halfword Algebraic with Update Indexed X 011111 01100 00011 / mtdcrx Move To Device Control Register Indexed X 011111 01100 10111 / sthx Store Halfword Indexed X 011111 01100 11100 0 orc OR with Complement X 011111 01100 11100 1 orc. OR with Complement and record CR X 011111 01101 10111 / sthux Store Halfword with Update Indexed X 011111 01101 11100 0 or OR X 011111 01101 11100 1 or. OR and record CR XFX 011111 01110 00011 / mtdcr Move To Device Control Register X 011111 01110 01011 0 divwu Divide Word Unsigned X 011111 01110 01011 1 divwu. Divide Word Unsigned and record CR XFX 011111 01110 10011 / mtspr Move To Special Purpose Register X 011111 01110 10110 / dcbi Data Cache Block Invalidate X 011111 01110 11100 0 nand NAND X 011111 01110 11100 1 nand. NAND and record CR X 011111 01111 01011 0 divw Divide Word X 011111 01111 01011 1 divw. Divide Word and record CR X 011111 10000 00000 / mcrxr Move to Condition Register from XER X 011111 10000 01000 0 subfco Subtract From Carrying and record OV X 011111 10000 01000 1 subfco. Subtract From Carrying and record OV and CR X 011111 10000 01010 0 addco Add Carrying and record OV X 011111 10000 01010 1 addco. Add Carrying and record OV and CR X 011111 10000 10101 / lswx Load String Word Indexed X 011111 10000 10110 / lwbrx Load Word Byte-Reverse Indexed X 011111 10000 10111 / lfsx Load Floating-Point Single Indexed Table 111. Instructions sorted by opcode (continued) Format Opcode Mnemonic Instruction Primary (Inst0:5) Extended (Inst21:31) |
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