AFBR-810BZ datasheet(24/48 Pages) AVAGO

24 / 48 page

Control Interface & Memory Map

The control interface combines dedicated signal lines for

address inputs, Adr[2:0], interrupt output, IntL, and reset

input, ResetL, with two-wire serial, TWS, interface clock,

SCL, and data, SDA, signals to provide users rich function-

ality over an efficient and easily used interface. The TWS

interface is implemented as a slave device and compatible

with industry standard two-wire serial protocol. It is scaled

for 3.3 volt LVTTL. Outputs are high-z in the high state to

support busing of these signals. Signal and timing char-

acteristics are further defined in the Control I/O Charac-

teristics section. In general, TWS bus timing and protocols

follow the implementation popularized in Atmel Two-

wire Serial EEPROMs. For additional details see, e.g., Atmel

AT24C01A.

The address signals, Adr2, Adr1 and Adr0, provide the

ability to program the TWS bus address of the module.

The module address has the binary form 0101hjkx, where

h, j and k correspond to Adr2, Adr1 and Adr0, respec-

tively and x corresponds to the Read/Write command bit.

Modules will respond to TWS bus addresses in the range

of 50h1 to 5Fh (hereafter 5ih) depending upon the state of

Adr2, Adr1 and Adr0. The address B0(h) should be avoided

on the TWS bus where these modules are used.

An interrupt signal, IntL, is used to alert the host of a loss

of input signal (LOS), transmitter fault conditions and/or

assertion of any monitor flag. This reduces the need for

dedicated status signal lines and polling the status and

monitor registers while maintaining timely alerts to sig-

nificant events. IntL can be programmed (page 01h byte

225 bit 0) to either pulse or static mode with pulse as the

default mode.

A dedicated module reset signal, ResetL, is provided in

case the TWS interface becomes dysfunctional. When

ResetL is asserted, the outputs are disabled, TWS interface

commands are inhibited and the module returns to

factory default settings except Non-volatile Read-Write

(RWn) registers which retain the last write. A module

reset can also be initiated over the TWS interface (page

5ih byte 91, bit 0). A TWS reset can be initiated by nine

SLA clock cycles with SDA high in each cycle and creating

a start condition.

With the TWS interface the user can read a status register

(page 5ih byte 2) to see if data is available in the monitor

registers, if the module has generated an IntL that has not

been cleared and global status reports for loss of signal

and fault conditions

LOS, Tx fault and/or monitor flag registers can be accessed

to check the status of individual channels or which channel

may have generated a recent IntL. LOS,Tx fault and flag bits

remain set (latched) after assertion even in the event the

condition changes and operation resumes until cleared

by the read operation of the associated registers or reset

by ResetL or the TWS module reset function.

The user can read the present value of the various monitors.

For transmitters and receivers, internal module temperature

and supply voltages are reported. For transmitters, monitors

provide for each channel laser bias current and laser light

output power (LOP) information. For receivers, input

power (Pave) is monitored for each channel. In addition,

elapsed operating time is reported. All monitor items are

two-byte fields and to maintain coherency, the host must

access these with single two-byte read sequences. For each

monitored item, alarm thresholds are established. If an item

moves past a threshold, a flag is set, and, provided the item

is not masked, IntL is asserted. The threshold settings are

available in the upper memory page, 01h.

The user can select either a pulse or static mode for the

interruptsignalIntLandinitiateamoduleregisterreset.The

user is provided the ability to disable individual channels.

For transmitters, equalization levels can be independently

set for individual channels. For receivers, output signal

amplitude, de-emphasis levels and rate select can be inde-

pendently set for individual channels. In the upper page,

01h, control field the user can invert the truth of the dif-

ferential inputs for individual transmitter channel and for

the differential outputs of individual receiver channels. In

addition, the user can disable the output squelch function

on an individual channel basis for both transmitters and

receivers. For transmitters the user can, on an individual

channel basis, activate a margin mode that reduces the

output optical modulation amplitude for the channel.

All non-volatile control registers are located in the upper

page 01(h). Non-volatile functions include the IntL mode

selection bit, input and output polarity flip bits, transmit-

ter equalization control bits, receiver output amplitude

control and receiver output de-emphasis control. Entries

into these registers will retain the last write for supply

voltage cycles and for ResetL and module register resets.

Volatile functions include module register reset, channel

disable, squelch disable and margin activation.

A mask bit that can be set to prevent assertion of IntL

for the individual item exists for every LOS, Tx fault and

monitor flag. Mask fields for LOS, Tx fault and module

monitors are in the lower memory page, 5ih, and the mask

field for the channel monitors are in the upper page 01h.

Entries in the mask fields are volatile.

Page 00h, based on the Serial ID pages of XFP and QSFP,

provides module identity and information regarding the

capabilities of the module.

1. In terms ##h, the h indicates that ## is hexadecimal, if ##b, b indicates binary and if ##, then decimal.

AFBR-810BZ Datasheet(PDF) 24 Page - AVAGO TECHNOLOGIES LIMITED

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