26

2. Memory Map Timing Characteristics

The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical

values are for Tc = 40°C, Vcc33 = 3.3 V and Vcc25 = 2.5 V.

Parameter

Symbol

Min

Typ

Units

Reference

Flag (including Tx Fault & LOS)

100

ms

Figure 20, Time from occurrence of condition to IntL

assertion, Vout:IntL = Vol

Flag (including Tx Fault & LOS)

100

ms

Figure 20, Time for clear on read operation, measured

from falling SCL edge after stop bit of read

transaction, until Vout:IntL = Voh, where IntL

is in static mode

Channel Disable Assert Time

100

ms

Figure 21, Time from write operation, measured from

falling edge of SCL after stop bit of write transaction,

until channel output falls below 10% of nominal

Channel Disable De-assert Time

300

ms

Figure 21, Time from write operation, measured from

falling edge of SCL after stop bit of write transaction,

until channel output rises above 90% of nominal

Mask Assert Time

100

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated IntL is inhibited

Mask De-assert Time

100

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated IntL resumes

Volatile Control Assert Time

(except Channel Disable)

100

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated control is activated

Volatile Control De-assert Time

(except Channel Disable)

100

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated control is de-activated

Control Transition Period

10

µs

Time during the control assert time when signal

integrity may be impaired

Non-Volatile Control Assert Time

150

ms

Time from up to two byte write operation, measured

from falling edge of SCL after stop bit of write

transaction, until associated control is activated

Non-Volatile Control De-assert

Time

150

ms

Time from up to two byte write operation, measured

from falling edge of SCL after stop bit of write

transaction, until associated control is de-activated

Non-Volatile Control Assert Time

300

ms

Time from up to six byte write operation, measured

from falling edge of SCL after stop bit of write

transaction, until associated control is activated

Non-Volatile Control De-assert

Time

300

ms

Time from up to six byte write operation, measured

from falling edge of SCL after stop bit of write

transaction, until associated control is de-activated

Module Reset Assert Time

100

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated reset begins

Module Reset De-assert Time

500

ms

Time from write operation, measured from falling

edge of SCL after stop bit of write transaction, until

associated reset is completed and normal operation

resumes

Notes:

1. Max values are valid where competing TWS traffic is absent.

2. The outputs of affected channels are disabled for incidences of Tx Fault and squelched for Tx LOS and/or Rx LOS. Timing for output fault and

squelch assertion and de-assertion are found in the Receiver Electrical and Transmitter Optical Characteristics sections.