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AFBR-810BZ Datasheet(PDF) 34 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-810BZ Datasheet(HTML) 34 Page - AVAGO TECHNOLOGIES LIMITED |
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34 / 48 page  34 5. Tx Memory Map 01h Upper Page Details of transmitter upper page 01h follow. Address Type Field Name/Description Byte Bit 128 all RO Internal Temperature High Alarm Threshold MSB: Integer part coded in signed 2’s complement 129 all RO Internal Temperature High Alarm Threshold LSB: Fractional part in units of 1°/256 coded in binary. 130 all RO Internal Temperature Low Alarm Threshold MSB: Integer part coded in signed 2’s complement 131 all RO Internal Temperature Low Alarm Threshold LSB: Fractional part in units of 1°/256 coded in binary. 132-143 all RO Reserved: Coded 00h 144-145 all RO Internal 3.3 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low address is MSB. 146-147 all RO Internal 3.3 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low address is MSB. 148-151 all RO Reserved 152-153 all RO Internal 2.5 Vcc High Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low address is MSB. 154-155 all RO Internal 2.5 Vcc Low Alarm Threshold: Voltage in 100 µV units coded as 16 bit unsigned integer, low address is MSB. 156-159 all RO Reserved 160-175 all RO Thresholds Reserved: Coded 00h 176-177 all RO Tx Bias Current All Channels High Alarm Threshold: Current in 2 µA units coded as 16 bit unsigned integer, low address is MSB. 178-179 all RO Tx Bias Current All Channels Low Alarm Threshold: Current in 2 µA units coded as 16 bit unsigned integer, low address is MSB. 180-183 all RO Reserved 184-185 all RO Tx Optical Power All Channels High Alarm Threshold: Optical power in 0.1 µW units coded as 16 bit unsigned integer, low address is MSB. 186-187 all RO Tx Optical Power All Channels Low Alarm Threshold: Optical power in 0.1 µW units coded as 16 bit unsigned integer, low address is MSB. 188-223 all RO Thresholds Reserved: Coded 00h 224 all RO Check sum: Low order 8 bits of the sum of all bytes from 128 through 223 inclusive 225 7-1 RWn Reserved: Coded 0000000b 225 0 RWn IntL Pulse/Static Option: Writing 1 sets IntL to Static mode, Default is 0 for Pulse mode 226 7-4 RWn Reserved: Coded 0000b 226 3 RWn Input Polarity Flip Channel 11: Writing 1 inverts truth of the differential input pair, Default is 0. 226 2 RWn Input Polarity Flip Channel 10: Writing 1 inverts truth of the differential input pair, Default is 0. 226 1 RWn Input Polarity Flip Channel 9: Writing 1 inverts truth of the differential input pair, Default is 0. 226 0 RWn Input Polarity Flip Channel 8: Writing 1 inverts truth of the differential input pair, Default is 0. 227 7 RWn Input Polarity Flip Channel 7: Writing 1 inverts truth of the differential input pair, Default is 0. 227 6 RWn Input Polarity Flip Channel 6: Writing 1 inverts truth of the differential input pair, Default is 0. 227 5 RWn Input Polarity Flip Channel 5: Writing 1 inverts truth of the differential input pair, Default is 0. 227 4 RWn Input Polarity Flip Channel 4: Writing 1 inverts truth of the differential input pair, Default is 0. 227 3 RWn Input Polarity Flip Channel 3: Writing 1 inverts truth of the differential input pair, Default is 0. 227 2 RWn Input Polarity Flip Channel 2: Writing 1 inverts truth of the differential input pair, Default is 0. 227 1 RWn Input Polarity Flip Channel 1: Writing 1 inverts truth of the differential input pair, Default is 0. 227 0 RWn Input Polarity Flip Channel 0: Writing 1 inverts truth of the differential input pair, Default is 0. 228 7-4 RWn Tx Input Equalization Control Channel 11: See below for code description. Default = 7 228 3-0 RWn Tx Input Equalization Control Channel 10: See below for code description. Default = 7 229 7-4 RWn Tx Input Equalization Control Channel 9: See below for code description. Default = 7 229 3-0 RWn Tx Input Equalization Control Channel 8: See below for code description. Default = 7 230 7-4 RWn Tx Input Equalization Control Channel 7: See below for code description. Default = 7 230 3-0 RWn Tx Input Equalization Control Channel 6: See below for code description. Default = 7 231 7-4 RWn Tx Input Equalization Control Channel 5: See below for code description. Default = 7 231 3-0 RWn Tx Input Equalization Control Channel 4: See below for code description. Default = 7 232 7-4 RWn Tx Input Equalization Control Channel 3: See below for code description. Default = 7 232 3-0 RWn Tx Input Equalization Control Channel 2: See below for code description. Default = 7 |
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