VP306 datasheet(8/85 Pages) MITEL

8 / 85 page

VP305/6

DRAFT - PRELIMINARY DATA

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

A system clock (SYS_CLK) running at twice the symbol data rate is provided by the VCO on the

VP216/7 ADC.

The dual ADC circuit digitises the In phase (I) and Quadrature phase (Q) analog signals providing

two, six bit binary offset, data channels. The code range is, from 000000 = least positive valid

output, to 111111 = most positive valid output.

These six bit data channels are input to the VP305/6 on the IIN and QIN pins to the QPSK

demodulator block, see figure 2 on page 9. There the data is decimated and filtered to obtain the

soft decision symbol data to pass to the Viterbi decoder. The QPSK block also generates a bit

clock and resolves the

π/2 demodulation phase ambiguity.

The Viterbi decoder recovers the data by a process of de-puncturing, probability analysis and bit

error correction, to obtain the eight bit wide, data bit stream. It also rearranges the bit stream into

bytes, providing a byte clock and packet start signal for the subsequent stages. An indication of

the bit error rate in the data, is provided in the Viterbi block, by comparing the delayed input data

bit stream with the decoded output data bit stream. An actual bit error count may be read from

registers and a coarse indication of the number of errors is provided to facilitate satellite receiver

dish alignment.

The data is then passed to the de-interleaver block where the data is reorganised in a series of

FIFOs into the 204 byte blocks for the Reed Solomon decoder. The de-interleaver depth is 12.

The Reed Solomon decoder is able to correct up to eight byte errors found in the byte data

stream. If there are too many errors to be corrected, the packet will be flagged as uncorrectable.

The 16 check bytes are removed and the 188 byte packet is passed to the next block.

The final data processing block removes Energy Dispersion and inverts the inverted packet

synchronisation byte which is used to mark every eighth 188 byte data packet.

The data output from the VP305/6 is in the form of MPEG2 transport stream data packets on the

MDO7:0 data bus, together with clock, data start, data valid and block error signals. The data rate

is automatically varied, according to the puncture rate, to reduce the instantaneous data rate and

the inter packet period.

VP306 Datasheet(PDF) 8 Page - Mitel Networks Corporation