VP306 datasheet(39/85 Pages) MITEL

39 / 85 page

DRAFT - PRELIMINARY DATA

VP305/6

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

The ± choice depends on the polarity of the VCO U/D signals. Select + if polarity is normal or - if

polarity is swapped (inverted). This is set by the CR_CONFIG[6] bit, see page 44.

The ramp times can be measured by observing the time intervals between the setting of interrupts

INT_QPSK[6] and INT_QPSK[7]. These interrupts are generated when the lower and upper

frequency limits are reached respectively, see page 27.

The relationship between the offset voltage and the CR_OFFSET parameter is as follows:

Voffset = ±

CR_OFFSET

32 * CR_KP

* VDD

See above for choice of ±.

2.7.3.2. Tracking Phase.

During the tracking phase, the mean value of the phase error should be zero. The mean value is

internally computed and subtracted from the phase error before the Sigma-Delta conversion. This

system is only operational in the tracking mode, set by CR_CONFIG[1] = 0, see page 44.

The maximum DC offset voltage which can be compensated by this method is:

Voffset_max = +

CR_OFFSET

32 * CR_KP

* VDD

e.g.

for VDD = 3.3v, CR_OFFSET = 127

For CR_KP = 255,

Voffset_max = 51mV (resolution 0.4mV)

For CR_KP = 30,

Voffset_max = 437mV (resolution 3.4mV)

2.7.4. CR_RP: Carrier reference period register.

Parallel mode -

Bank 2. Address 4.

Type Read / Write.

Serial mode - Address 20.

7654

3210

Reserved

CR_RP[3:0] Carrier reference period

CR_RP[3:0]

Carrier frequency reference period for the count of the crystal clock cycles ( XTI

pin). This sets the reference for the measurement of the I/Q down converter

VCO frequency (PSCAL pins). The register value sets the 4 most significant bits

of a 14 bit counter. The actual count is CR_RP[3:0] * 1024. See page 12 for

further discussion.

VP306 Datasheet(PDF) 39 Page - Mitel Networks Corporation

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