VP306 datasheet(28/85 Pages) MITEL

28 / 85 page

VP305/6

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2.5.3. INT_FEC: Interrupt FEC register.

These bits indicate the FEC block event causing the interrupt signalled by the IRQ line going

low. The IRQ line is reset high and the register is reset to zero when it is read. The events can

be masked from activating the

IRQ

line by setting the appropriate event masking bit in the

IE_FEC (interrupt enable) FEC register, see page 52. The masking of events does not affect the

setting of the bits in the INT_FEC register.

Parallel mode -

Bank 0. Address 2.

Type Read.

Serial mode - Address 02.

76543210

INT_FEC[7:0]

INT_FEC[0]

High = Descrambler lock established.

INT_FEC[1]

High = Descrambler lock is lost.

INT_FEC[2]

High = Viterbi error monitor period has reached the value programmed in the

VMERR[7:0] register.

INT_FEC[3]

Reserved.

INT_FEC[4]

High = Viterbi bit lock established.

INT_FEC[5]

High = Viterbi bit lock is lost.

INT_FEC[6]

High = Frame alignment lock established. (A Frame is 8 blocks, each block is 204

bytes).

INT_FEC[7]

High = Frame alignment lock is lost.

VP306 Datasheet(PDF) 28 Page - Mitel Networks Corporation