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VP306 Datasheet(PDF) 21 Page - Mitel Networks Corporation |
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VP306 Datasheet(HTML) 21 Page - Mitel Networks Corporation |
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21 / 85 page ![]() DRAFT - PRELIMINARY DATA VP305/6 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 21 NAME ADR D7D6D5D4D3D2 D1D0 R/W ID 0 ID[7:0] Chip identification R SCALE 1 SCALE[7:0] Scale factor for IOUT and QOUT outputs R/W SNR_THS 2 SNR_THS[7:0] SNR estimator threshold R/W CR_OFFSET 3 CR_OFFSET[7:0] Carrier loop DC offset compensation value R/W CR_RP 4 Reserved CR_RP[3:0] Carrier reference period R/W CR_KP 5 CR_KP[7:0] Carrier loop filter gain (P term) R/W CR_KD 6 CR_KD[7:0] Carrier loop filter gain (D term) R/W CR_THSL 7 CR_THSL[7:0] Carrier lock detector threshold R/W Table 5d Register bank 2. BANK[5:3] = 16. NAME ADR D7D6D5D4D3D2 D1D0 R/W ID 0 ID[7:0] Chip identification R CR_SWR 1 CR_SWR[7:0] Carrier sweep rate R/W CR_USWL U 2 Reserved CR_USWL[13:8] Carrier Upper sweep limit (upper nibble) R/W CR_USWL L 3 CR_USWL[7:0] Carrier Upper sweep limit (lower byte) R/W CR_LSWL U 4 Reserved CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) R/W CR_LSWL L 5 CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) R/W CR_CONFIG 6 CR_CONFIG[7:0] Carrier configuration R/W CONFIG 7 CONFIG[7:0] Configuration R/W Table 5e. Register bank 3. BANK[5:3] = 24. NAME ADR D7D6D5D4D3D2 D1D0 R/W ID 0 ID[7:0] Chip identification R VIT_ERR_C H 1 VERRC[15:8] - Viterbi error count high byte R VIT_ERR_C L 2 VERRC[7:0] - Viterbi error count low byte R RS_UBC 3 RSUBC[7:0] - Reed Solomon uncorrected block count R Not used 4 - 7 Writing to these addresses will have no effect. Reading will return 255 R/W Table 5f. Register bank 4. BANK[5:3] = 32. Note: In Bank 4, the registers 1 to 3 are READ only and registers 4 to 7 are not used. Writing to these addresses will have no effect. |
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