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VP306 Datasheet(PDF) 7 Page - Mitel Networks Corporation

Part # VP306
Description  Satellite Channel Decoder
PDF  85 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

VP306 Datasheet(HTML) 7 Page - Mitel Networks Corporation

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DRAFT - PRELIMINARY DATA
VP305/6
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
7
PLEASE NOTE:
This manual has the following convention:
All numerical values are shown as decimal numbers, unless otherwise defined.
1.
FUNCTIONAL DESCRIPTION.
QPSK
De-inter
leaver
Viterbi
Reed
Solomon
Energy
Dispersal
Test
Microprocessor
Interface
Timing / sync
PSCAL
SYS_CLK
IIN5:0
QIN5:0
3
3
SYMCLK
8
8
8
MDOEN
MDO7:0
XTI
XTO
XTCK
IRQ
DTACK
D7:0
SDA
A2:0
R/W
AS CS
SER
GPP0
RESET
RES
INTQP
INTVI
MCLK
MOSTRT
CR_VCO
AGC_OUT
SYM_VCO
2
2
2
BKERR
GPP4:1
4
VERR
MOVAL
Clock
STATUS
TEST1
TEST2
TEST3
Fig. 1. VP305/6 Block Diagram.
1.1.
System overview.
The VP305/6 decoder, together with the SL1710 I/Q down converter and the VP216/7 dual analog
to digital converter (ADC) devices will provide a DVB compliant, satellite receiver system, see
figure 2 on page 9. Before transmission, the data is processed using forward error correction
techniques. Energy dispersal is added to even out 'ones' and 'zeros' for the power handling of the
satellite output transmission devices. The VP305/6 device decodes the signal by reversing all
these encoding techniques.
The VP305/6 contains three phase lock loop systems for control of the voltage controlled
oscillators in the SL1710, the VP216/7 and an internal numerically controlled oscillator (NCO) in
the VP305/6. The NCO can be set to provide a triangular wave form frequency search to establish
symbol lock. There are also two AGC systems in the VP305/6, one controlling the SL1710 gain
and a second internal AGC control of the output power levels from the QPSK block to the Viterbi
block.
A crystal oscillator maintaining circuit is provided to sustain a stable frequency reference clock for
the synthesiser loops. If a crystal is not used, the reference frequency signal may be input on the
XTI pin.



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