VP306 datasheet(44/85 Pages) MITEL

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VP305/6

DRAFT - PRELIMINARY DATA

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on the title page of this document.

2.8.3. CR_LSWL U & L: Carrier Lower sweep limit registers.

Parallel mode -

Bank 3. Addresses 4, 5.

Type Read / Write.

Serial mode - Addresses 28, 28.

6543210

Reserved

CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble)

CR_LSWL[7:0] Carrier Lower sweep limit (lower byte)

These two bytes together form the 14 bit number: CR_LSWL[13:0] Carrier Lower sweep limit. This

is the division ratio (lower) for the prescaler input (PSCAL) from the SL1710.

2.8.4. CR_CONFIG: Carrier configuration register.

Parallel mode -

Bank 3. Address 6.

Type Read / Write.

Serial mode - Address 30.

6543210

CR_CONFIG[7:0] Carrier configuration

CR_CONFIG[0]

CR_SW

High = carrier loop sweep on.

Low = carrier loop sweep off.

CR_CONFIG[1]

CR_OPEN

High = carrier loop open. This is only used to get out of a false lock.

Low = carrier loop closed.

CR_CONFIG[2]

CR_PED_SEL Carrier phase error detector select.

High = NDAML Non-data aided maximum likelihood estimator (only available in

QPSK mode).

Low = DDML Decision directed maximum likelihood estimator.

CR_CONFIG[3]

Reserved set low.

CR_CONFIG[4]

CR_VCO1 D/U

High = tri-state D and U outputs.

Low = active outputs.

CR_CONFIG[5]

CR_VCO2 D/U

High = tri-state D and U outputs.

Low = active outputs.

CR_CONFIG[6]

CR_VCO_SWAP exchange polarity for both CR_VCO1 and CR_VCO2 D

and U outputs.

High = swapped (i.e. D and U inverted).

Low = normal.

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